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Luis Entrena: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
    Functional extension of structural logic optimization techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:467-472 [Conf]
  2. Luis Berrojo, I. Gónzólez, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
    New Techniques for Speeding-Up Fault-Injection Campaigns. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:847-853 [Conf]
  3. José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
    Generalized reasoning scheme for redundancy addition and removal logic optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:391-397 [Conf]
  4. Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno
    Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:516-520 [Conf]
  5. Enrique San Millán, Luis Entrena, José Alberto Espejo
    On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:292-299 [Conf]
  6. Raul Sánchez-Reillo, Judith Liu-Jimenez, Luis Entrena
    Architectures for Biometric Match-on-Token Solutions. [Citation Graph (0, 0)][DBLP]
    ECCV Workshop BioAW, 2004, pp:195-204 [Conf]
  7. José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
    Logic Restructuring for MUX-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1161-0 [Conf]
  8. Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena
    FPGA Implementation of Biometric Authentication System Based on Hand Geometry. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:43-53 [Conf]
  9. Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo
    Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:220-229 [Conf]
  10. Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena
    Power Consumption Reduction Through Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:751-760 [Conf]
  11. Almudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez
    Correlation-Based Fingerprint Matching Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:87-94 [Conf]
  12. Luis Entrena, Kwang-Ting Cheng
    Sequential logic optimization by redundancy addition and removal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:310-315 [Conf]
  13. Enrique San Millán, Luis Entrena, José Alberto Espejo
    On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:91-94 [Conf]
  14. Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena
    Transient Fault Emulation of Hardened Circuits in FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:109-114 [Conf]
  15. Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:193- [Conf]
  16. Luis Entrena, Celia López, Emilio Olías
    Automatic Insertion of Fault-Tolerant Structures at the RT Level. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:48-50 [Conf]
  17. Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo
    Logic Optimization of Unidirectional Circuits with Structural Methods. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:43-47 [Conf]
  18. Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena
    Emulation-based Fault Injection in Circuits with Embedded Memories. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:183-184 [Conf]
  19. Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo
    State Encoding for Low-Power FSMs in FPGA. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:31-40 [Conf]
  20. Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
    An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:229-236 [Conf]
  21. Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López
    Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:529-541 [Journal]
  22. Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez
    Wavelet-Based Fingerprint Region Selection. [Citation Graph (0, 0)][DBLP]
    CAIP, 2007, pp:391-398 [Conf]
  23. Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán
    Correlation-Based Fingerprint Matching with Orientation Field Alignment. [Citation Graph (0, 0)][DBLP]
    ICB, 2007, pp:713-721 [Conf]
  24. Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
    A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:101-106 [Conf]
  25. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
    Fault Injection-based Reliability Evaluation of SoPCs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:75-82 [Conf]
  26. Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena
    Low power data processing system with self-reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:9, pp:568-576 [Journal]

  27. SET Emulation Under a Quantized Delay Model. [Citation Graph (, )][DBLP]


  28. Logic Transformations by Multiple Wire Network Addition. [Citation Graph (, )][DBLP]


  29. An effective system development environment based on VHDL prototyping. [Citation Graph (, )][DBLP]


  30. Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. [Citation Graph (, )][DBLP]


  31. Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. [Citation Graph (, )][DBLP]


  32. Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. [Citation Graph (, )][DBLP]


  33. In-depth analysis of digital circuits against soft errors for selective hardening. [Citation Graph (, )][DBLP]


  34. Briefing power/reliability optimization in embedded software design. [Citation Graph (, )][DBLP]


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