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Viraphol Chaiyakul: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nong Fan, Viraphol Chaiyakul, Daniel Gajski
    Usage-based characterization of complex functional blocks for reuse in behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:43-48 [Conf]
  2. Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud
    Embedded tutorial: essential issues for IP reuse. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:37-42 [Conf]
  3. Viraphol Chaiyakul, Daniel Gajski, Loganath Ramachandran
    High-Level Transformations for Minimizing Syntactic Variances. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:413-418 [Conf]
  4. Loganath Ramachandran, Daniel Gajski, Viraphol Chaiyakul
    An Algorithm for Array Variable Clustering. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:262-266 [Conf]
  5. Hsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski
    Condition graphs for high-quality behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:170-174 [Conf]
  6. Hsiao-Ping Juan, Daniel Gajski, Viraphol Chaiyakul
    Clock-driven performance optimization in interactive behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:154-157 [Conf]
  7. Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul
    Accurate layout area and delay modeling for system level design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:355-361 [Conf]
  8. Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski
    Layout-Area Models for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:34-37 [Conf]

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