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Allen C.-H. Wu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu
    A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:351-354 [Conf]
  2. Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee
    EMPAR: an interactive synthesis environment for hardware emulations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud
    Embedded tutorial: essential issues for IP reuse. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:37-42 [Conf]
  4. Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu
    An RTL design-space exploration method for high-level applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:162-168 [Conf]
  5. Wen-Jong Fang, Allen C.-H. Wu
    Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:518-521 [Conf]
  6. Wen-Jong Fang, Allen C.-H. Wu
    Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:283-286 [Conf]
  7. Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen
    A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:101-106 [Conf]
  8. Yuh-Sheng Lee, Allen C.-H. Wu
    A Performance and Routability Driven Router for FPGAs Considering Path Delays. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:557-561 [Conf]
  9. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:262-267 [Conf]
  10. Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
    G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11134-11135 [Conf]
  11. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
    Decomposition of Instruction Decoder for Low Power Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:664-665 [Conf]
  12. Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
    A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11102-11103 [Conf]
  13. Tsung-Yi Wu, Tzu-Chie Tien, Allen C.-H. Wu, Youn-Long Lin
    A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:277-281 [Conf]
  14. Kun-Ming Ho, Allen C.-H. Wu
    Module Generation of High Performance FPGA-Based Multipliers. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:251- [Conf]
  15. Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
    Module Generation of Complex Macros for Logic-Emulation Applications. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:69-75 [Conf]
  16. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-optimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:123-127 [Conf]
  17. Wen-Jong Fang, Allen C.-H. Wu
    A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:638-643 [Conf]
  18. Chi-Hong Hwang, Allen C.-H. Wu
    A predictive system shutdown method for energy saving of event-driven computation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:28-32 [Conf]
  19. Chien-Chu Kuo, Allen C.-H. Wu
    Delay Budgeting for a Timing-Closure-Driven Design Method. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:202-207 [Conf]
  20. Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin
    An effective methodology for functional pipelining. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:230-233 [Conf]
  21. Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul
    Accurate layout area and delay modeling for system level design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:355-361 [Conf]
  22. Allen C.-H. Wu, Daniel Gajski
    Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:144-147 [Conf]
  23. Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski
    Layout-Area Models for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:34-37 [Conf]
  24. Allen C.-H. Wu, Tedd Hadley, Daniel Gajski
    An efficient multi-view design model for real-time interactive synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:328-331 [Conf]
  25. Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    State Assignment for Power and Area Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:250-254 [Conf]
  26. M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu
    A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:81-84 [Conf]
  27. J. C.-Y. Kao, C.-F. Su, Allen C.-H. Wu
    High-performance FIR generation based on a timing-driven architecture and component selection method. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:759-762 [Conf]
  28. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:12-17 [Conf]
  29. Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin
    Preserving HDL synthesis hierarchy for cell placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:169-174 [Conf]
  30. Bing-Fei Wu, Chuan-Tsai Lin, Chao-Jung Chen, Tze-Chiuan Lai, Hsueh-Lung Liao, Allen C.-H. Wu
    A fast lane and vehicle detection approach for autonomous vehicles. [Citation Graph (0, 0)][DBLP]
    SIP, 2005, pp:305-310 [Conf]
  31. Wen-Jong Fang, Allen C.-H. Wu
    Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:2, pp:65-72 [Journal]
  32. Tsing-Gen Lee, Wen-Jong Fang, Allen C.-H. Wu
    The Design and Inplementation of a Cooperative Design-view Environment for Interactive Partitioning Applications. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1996, v:26, n:10, pp:1141-1160 [Journal]
  33. Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin
    TRACER-fpga: a router for RAM-based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:371-374 [Journal]
  34. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-minimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1076-1084 [Journal]
  35. Wen-Jong Fang, Allen C.-H. Wu
    A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1188-1195 [Journal]
  36. Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu
    Layout placement for sliced architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:102-114 [Journal]
  37. Yuh-Sheng Lee, Allen C.-H. Wu
    A performance and routability-driven router for FPGAs considering path delays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:2, pp:179-185 [Journal]
  38. Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
    A transformation-based method for loop folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:439-450 [Journal]
  39. Allen C.-H. Wu, Daniel D. Gajski
    Partitioning algorithms for layout synthesis from register-transfer netlists. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:453-463 [Journal]
  40. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:475-483 [Journal]
  41. Wen-Jong Fang, Allen C.-H. Wu
    Multiway FPGA partitioning by fully exploiting design hierarchy. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:34-50 [Journal]
  42. Chi-Hong Hwang, Allen C.-H. Wu
    A predictive system shutdown method for energy saving of event-driven computation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:2, pp:226-241 [Journal]
  43. Yann-Rue Lin, Cheng-Tsung Hwang, Allen C.-H. Wu
    Scheduling techniques for variable voltage low power designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:2, pp:81-97 [Journal]
  44. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
    Decomposition of instruction decoders for low-power designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:4, pp:880-889 [Journal]
  45. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
    A power-driven multiplication instruction-set design method for ASIPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:81-85 [Journal]
  46. Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
    Performance-driven crosstalk elimination at post-compiler level. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  47. Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
    EmGen-a module generator for logic emulation applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:488-492 [Journal]
  48. Allen C.-H. Wu, Nikil D. Dutt
    Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:469-471 [Journal]

  49. A new algorithm for transistor sizing in CMOS circuits. [Citation Graph (, )][DBLP]


  50. A power-driven multiplication instruction-set design method for ASIPs. [Citation Graph (, )][DBLP]


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