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Elena Dubrova :
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Petra Färm , Elena Dubrova , Andreas Kuehlmann Logic optimization using rule-based randomized search. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:998-1001 [Conf ] René Krenz , Elena Dubrova A fast algorithm for finding common multiple-vertex dominators in circuit graphs. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:529-532 [Conf ] René Krenz , Elena Dubrova Improved Boolean function hashing based on multiple-vertex dominators. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:573-578 [Conf ] Andrés Martinelli , René Krenz , Elena Dubrova Disjoint-support Boolean decomposition combining functional and structural methods. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2004, pp:597-599 [Conf ] Elena Dubrova Composition Trees in Finding Best Variable Orderings for ROBDDs. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:1084- [Conf ] Elena Dubrova Structural Testing Based on Minimum Kernels. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:1168-1173 [Conf ] Elena Dubrova , Peeter Ellervee , D. Michael Miller , Jon C. Muzio TOP: An Algorithm for Three-Level Optimization of PLDs. [Citation Graph (0, 0)][DBLP ] DATE, 2000, pp:751- [Conf ] Andrés Martinelli , Elena Dubrova Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:430-431 [Conf ] Maxim Teslenko , Elena Dubrova An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:406-411 [Conf ] Jimson Mathew , Elena Dubrova Self-Checking 1-out-of-n CMOS Current-Mode Checker. [Citation Graph (0, 0)][DBLP ] DFT, 2002, pp:69-77 [Conf ] Elena Dubrova , Maxim Teslenko , Hannu Tenhunen Computing attractors in dynamic networks. [Citation Graph (0, 0)][DBLP ] IADIS AC, 2005, pp:535-542 [Conf ] Elena Dubrova , Maxim Teslenko , Andrés Martinelli Kauffman networks: analysis and applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:479-484 [Conf ] Maxim Teslenko , Elena Dubrova Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:748-751 [Conf ] Elena Dubrova , Maxim Teslenko , Johan Karlsson Boolean Decomposition Based on Cyclic Chains. [Citation Graph (0, 0)][DBLP ] ICCD, 2003, pp:504-509 [Conf ] Elena Dubrova Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2005, pp:2212-2215 [Conf ] Elena Dubrova , Maxim Teslenko , Andrés Martinelli On relation between non-disjoint decomposition and multiple-vertex dominators. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2004, pp:493-496 [Conf ] Imed Ben Dhaou , Elena Dubrova , Hannu Tenhunen Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology. [Citation Graph (0, 0)][DBLP ] ISMVL, 2001, pp:61-66 [Conf ] Elena Dubrova Implementation of Multiple-Valued Functions Using Literal-Splitting Technique. [Citation Graph (0, 0)][DBLP ] ISMVL, 2003, pp:7-10 [Conf ] Elena Dubrova A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 2004, pp:309-314 [Conf ] Elena Dubrova Random Multiple-Valued Networks: Theory and Applications. [Citation Graph (0, 0)][DBLP ] ISMVL, 2006, pp:27- [Conf ] Elena Dubrova Evaluation of m-Valued Fixed Polarity Generalizations of Reed-Muller Canonical Form. [Citation Graph (0, 0)][DBLP ] ISMVL, 1999, pp:92-98 [Conf ] Elena Dubrova , Petra Färm A Conjunctive Canonical Expansion of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 2002, pp:35-38 [Conf ] Elena Dubrova , Dilian Gurov , Jon C. Muzio Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP ] ISMVL, 1994, pp:284-288 [Conf ] Elena Dubrova , Dilian Gurov , Jon C. Muzio The Evaluation of Full Sensitivity for Test Generation in MVL Circuits. [Citation Graph (0, 0)][DBLP ] ISMVL, 1995, pp:104-0 [Conf ] Elena Dubrova , Jon C. Muzio Testability of Generalized Multiple-Valued Reed-Muller Circuits. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:56-61 [Conf ] Elena Dubrova , Jon C. Muzio , Bernhard von Stengel Finding Composition Trees for Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1997, pp:19-26 [Conf ] Elena Dubrova , Harald Sack Probabilistic Verification of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 2000, pp:460-466 [Conf ] René Krenz , Elena Dubrova , Andreas Kuehlmann Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation. [Citation Graph (0, 0)][DBLP ] ISMVL, 2003, pp:334-0 [Conf ] Harald Sack , Elena Dubrova , Christoph Meinel Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 2000, pp:233-238 [Conf ] Tomas Bengtsson , Andrés Martinelli , Elena Dubrova A Fast Heuristic Algorithm for Disjunctive. [Citation Graph (0, 0)][DBLP ] IWLS, 2002, pp:51-56 [Conf ] Petra Färm , Elena Dubrova Technology Mapping for Chemically Assembled Electronic Nanotechnology. [Citation Graph (0, 0)][DBLP ] IWLS, 2002, pp:121-124 [Conf ] René Krenz , Elena Dubrova , Andreas Kuehlmann Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions. [Citation Graph (0, 0)][DBLP ] IWLS, 2002, pp:321-326 [Conf ] Hannu Tenhunen , Elena Dubrova SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH. [Citation Graph (0, 0)][DBLP ] MSE, 2001, pp:64-66 [Conf ] Elena Dubrova , Jon C. Muzio Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2000, v:49, n:11, pp:1285-1289 [Journal ] Elena Dubrova , Luca Macchiarulo A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2000, v:49, n:11, pp:1290-1292 [Journal ] Maxim Teslenko , Andrés Martinelli , Elena Dubrova Bound-Set Preserving ROBDD Variable Orderings May Not Be Optimum. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2005, v:54, n:2, pp:236-237 [Journal ] On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers. [Citation Graph (, )][DBLP ] How to speed-up your NLFSR-based stream cipher. [Citation Graph (, )][DBLP ] Evaluation and Comparison of Threshold Logic Gates. [Citation Graph (, )][DBLP ] Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-Based Bounded Model Checking. [Citation Graph (, )][DBLP ] Self-Organization for Fault-Tolerance. [Citation Graph (, )][DBLP ] An equivalence preserving transformation from the Fibonacci to the Galois NLFSRs [Citation Graph (, )][DBLP ] Finding matching initial states for equivalent NLFSRs in the fibonacci and the galois configurations [Citation Graph (, )][DBLP ] An Improved Implementation of Grain [Citation Graph (, )][DBLP ] Search in 0.006secs, Finished in 0.008secs