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Andreas Kuehlmann :
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Petra Färm , Elena Dubrova , Andreas Kuehlmann Logic optimization using rule-based randomized search. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:998-1001 [Conf ] Jason Baumgartner , Andreas Kuehlmann , Jacob A. Abraham Property Checking via Structural Analysis. [Citation Graph (0, 0)][DBLP ] CAV, 2002, pp:151-165 [Conf ] Andreas Kuehlmann , Jason Baumgartner Transformation-Based Verification Using Generalized Retiming. [Citation Graph (0, 0)][DBLP ] CAV, 2001, pp:104-117 [Conf ] Nina Amla , Xiaoqun Du , Andreas Kuehlmann , Robert P. Kurshan , Kenneth L. McMillan An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment. [Citation Graph (0, 0)][DBLP ] CHARME, 2005, pp:254-268 [Conf ] Reinaldo A. Bergamaschi , Donald Lobo , Andreas Kuehlmann Control Optimization in High-Level Synthesis Using Behavioral Don't Cares. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:657-661 [Conf ] Donald Chai , Andreas Kuehlmann A fast pseudo-boolean constraint solver. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:830-835 [Conf ] Malay K. Ganai , Adnan Aziz , Andreas Kuehlmann Enhancing Simulation with BDDs and ATPG. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:385-390 [Conf ] Andreas Kuehlmann , David Ihsin Cheng , Arvind Srinivasan , David P. LaPotin Error Diagnosis for Transistor-Level Verification. [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:218-224 [Conf ] Andreas Kuehlmann , Malay K. Ganai , Viresh Paruthi Circuit-based Boolean Reasoning. [Citation Graph (0, 0)][DBLP ] DAC, 2001, pp:232-237 [Conf ] Andreas Kuehlmann , Florian Krohm Equivalence Checking Using Cuts and Heaps. [Citation Graph (0, 0)][DBLP ] DAC, 1997, pp:263-268 [Conf ] Qi Zhu , Nathan Kitchen , Andreas Kuehlmann , Alberto L. Sangiovanni-Vincentelli SAT sweeping with local observability don't-cares. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:229-234 [Conf ] Jason Baumgartner , Andreas Kuehlmann Enhanced Diameter Bounding via Structural. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:36-41 [Conf ] Donald Chai , Andreas Kuehlmann Building a better Boolean matcher and symmetry detector. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:1079-1084 [Conf ] Hari Mony , Jason Baumgartner , Viresh Paruthi , Robert Kanzelman , Andreas Kuehlmann Scalable Automated Verification via Expert-System Guided Transformations. [Citation Graph (0, 0)][DBLP ] FMCAD, 2004, pp:159-173 [Conf ] Jason Baumgartner , Andreas Kuehlmann Min-Area Retiming on Dynamic Circuit Structures. [Citation Graph (0, 0)][DBLP ] ICCAD, 2001, pp:176-182 [Conf ] Aaron P. Hurst , Philip Chong , Andreas Kuehlmann Physical placement driven by sequential timing analysis. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:379-386 [Conf ] Andreas Kuehlmann Dynamic transition relation simplification for bounded property checking. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:50-57 [Conf ] Andreas Kuehlmann , Reinaldo A. Bergamaschi Timing analysis in high-level synthesis. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:349-354 [Conf ] Andreas Kuehlmann , Robert W. Dutton , Paul D. Franzon , Seth Copen Goldstein , Philip Luekes , Eric Parker , Thomas N. Theis Will Nanotechnology Change the Way We Design and Verify Systems? (Panel). [Citation Graph (0, 0)][DBLP ] ICCAD, 2001, pp:174- [Conf ] Andreas Kuehlmann , Kenneth L. McMillan , Robert K. Brayton Probabilistic state space search. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:574-579 [Conf ] Cong Liu , Andreas Kuehlmann , Matthew W. Moskewicz CAMA: A Multi-Valued Satisfiability Solver. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:326-333 [Conf ] Kaushik Ravindran , Andreas Kuehlmann , Ellen Sentovich Multi-Domain Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:801-808 [Conf ] Subarnarekha Sinha , Andreas Kuehlmann , Robert K. Brayton Sequential SPFDs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2001, pp:84-90 [Conf ] Donald Chai , Andreas Kuehlmann Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation. [Citation Graph (0, 0)][DBLP ] ICCD, 2004, pp:387-392 [Conf ] Nathan Kitchen , Andreas Kuehlmann Temporal Decomposition for Logic Optimization. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:697-702 [Conf ] Florian Krohm , Andreas Kuehlmann , Arjen Mets The use of random simulation in formal verification. [Citation Graph (0, 0)][DBLP ] ICCD, 1996, pp:371-0 [Conf ] Andreas Kuehlmann , Reinaldo A. Bergamaschi High-Level State Machine Specification and Synthesis. [Citation Graph (0, 0)][DBLP ] ICCD, 1992, pp:536-539 [Conf ] Andreas Kuehlmann , Lukas P. P. P. van Ginneken Grammar-Based Optimization of Synthesis Scenarios. [Citation Graph (0, 0)][DBLP ] ICCD, 1994, pp:20-25 [Conf ] Viresh Paruthi , Andreas Kuehlmann Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. [Citation Graph (0, 0)][DBLP ] ICCD, 2000, pp:459-464 [Conf ] Guoqiang Wang , Andreas Kuehlmann , Alberto L. Sangiovanni-Vincentelli Structural Detection of Symmetries in Boolean Functions. [Citation Graph (0, 0)][DBLP ] ICCD, 2003, pp:498-503 [Conf ] René Krenz , Elena Dubrova , Andreas Kuehlmann Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation. [Citation Graph (0, 0)][DBLP ] ISMVL, 2003, pp:334-0 [Conf ] Zhong Xiu , David A. Papa , Philip Chong , Christoph Albrecht , Andreas Kuehlmann , Rob A. Rutenbar , Igor L. Markov Early research experience with OpenAccess gear: an open source development environment for physical design. [Citation Graph (0, 0)][DBLP ] ISPD, 2005, pp:94-100 [Conf ] Zile Wei , Donald Chai , A. Richard Newton , Andreas Kuehlmann Fast Boolean Matching with Don't Cares. [Citation Graph (0, 0)][DBLP ] ISQED, 2006, pp:346-351 [Conf ] René Krenz , Elena Dubrova , Andreas Kuehlmann Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions. [Citation Graph (0, 0)][DBLP ] IWLS, 2002, pp:321-326 [Conf ] HoonSang Jin , Andreas Kuehlmann , Fabio Somenzi Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis. [Citation Graph (0, 0)][DBLP ] TACAS, 2002, pp:312-326 [Conf ] Farhana Sheikh , Andreas Kuehlmann , Kurt Keutzer Minimum-power retiming for dual-supply CMOS circuits. [Citation Graph (0, 0)][DBLP ] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:43-49 [Conf ] Rajiv V. Joshi , Wei Hwang , Andreas Kuehlmann Design Of Provably Correct Storage Arrays. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2001, pp:196-0 [Conf ] Andreas Kuehlmann Integrated Design Flows - A Battered EDA Slogan or True Challenge for Tool Development and Algorithmic Research. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:41- [Conf ] John Willis , Andreas Kuehlmann Design Automation TC Newsletter. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:2, pp:166-0 [Journal ] Sérgio Vale Aguiar Campos , Marcio Teixeira , Marius Minea , Andreas Kuehlmann , Edmund M. Clarke Model Checking Semi-Continuous Time Models Using BDDs. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 1999, v:23, n:2, pp:- [Journal ] Donald Chai , Andreas Kuehlmann A fast pseudo-Boolean constraint solver. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:305-317 [Journal ] Andreas Kuehlmann , Viresh Paruthi , Florian Krohm , Malay K. Ganai Robust Boolean reasoning for equivalence checking and functional property verification. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1377-1394 [Journal ] Satrajit Chatterjee , Alan Mishchenko , Robert K. Brayton , Andreas Kuehlmann On Resolution Proofs for Combinational Equivalence. [Citation Graph (0, 0)][DBLP ] DAC, 2007, pp:600-605 [Conf ] Reinaldo A. Bergamaschi , Andreas Kuehlmann A system for production use of high-level synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:233-243 [Journal ] A Markov Chain Monte Carlo Sampler for Mixed Boolean/Integer Constraints. [Citation Graph (, )][DBLP ] Generalizing DPLL to Richer Logics. [Citation Graph (, )][DBLP ] Verifying really complex systems: on earth and beyond. [Citation Graph (, )][DBLP ] Next generation wireless-multimedia devices: who is up for the challenge? [Citation Graph (, )][DBLP ] Guess, solder, measure, repeat: how do I get my mixed-signal chip right? [Citation Graph (, )][DBLP ] EDA in flux: should I stay or should I go? [Citation Graph (, )][DBLP ] Does IC design have a future in the clouds? [Citation Graph (, )][DBLP ] Stimulus generation for constrained random simulation. [Citation Graph (, )][DBLP ] SAT-based protein design. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.007secs