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Title:
Author:
Niraj K. Jha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yunsi Fei, Niraj K. Jha
    Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:274-281 [Conf]
  2. Jiong Luo, Niraj K. Jha
    Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:719-728 [Conf]
  3. Li Shang, Niraj K. Jha
    Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:345-354 [Conf]
  4. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Embedded Software Synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:711-718 [Conf]
  5. Lin Zhong, Niraj K. Jha
    Graphical user interface energy characterization for handheld computers. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:232-242 [Conf]
  6. Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Enhancing security through hardware-assisted run-time validation of program data properties. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:190-195 [Conf]
  7. Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Architectural support for safe software execution on embedded processors. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:106-111 [Conf]
  8. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:601-605 [Conf]
  9. Keith S. Vallerio, Niraj K. Jha
    Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:63-69 [Conf]
  10. Keith S. Vallerio, Niraj K. Jha
    Language Selection for Mobile Systems: Java, C, or Both? [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:185-191 [Conf]
  11. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:496-501 [Conf]
  12. Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
    COSYN: Hardware-Software Co-Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:703-708 [Conf]
  13. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Power analysis of embedded operating systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:312-315 [Conf]
  14. Indradeep Ghosh, Sujit Dey, Niraj K. Jha
    A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:542-547 [Conf]
  15. Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
    A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:554-559 [Conf]
  16. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:534-539 [Conf]
  17. Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Efficient fingerprint-based user authentication for embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:244-247 [Conf]
  18. Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha
    HybDTM: a coordinated hardware-software approach for dynamic thermal management. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:548-553 [Conf]
  19. Ganesh Lakshminarayana, Niraj K. Jha
    FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:102-107 [Conf]
  20. Ganesh Lakshminarayana, Niraj K. Jha
    Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:439-444 [Conf]
  21. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:108-113 [Conf]
  22. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-Case Computation: A High-Level Technique for Power and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:56-61 [Conf]
  23. Tien-Chien Lee, Niraj K. Jha, Wayne Wolf
    Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:292-297 [Conf]
  24. Jiong Luo, Niraj K. Jha
    Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:444-449 [Conf]
  25. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Automated energy/performance macromodeling of embedded software. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:99-102 [Conf]
  26. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Hybrid simulation for embedded software energy estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:23-26 [Conf]
  27. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    Glitch Analysis and Reduction in Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:331-336 [Conf]
  28. Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
    Power Management Techniques for Control-Flow Intensive Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:429-434 [Conf]
  29. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    High-level Software Energy Macro-modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:605-610 [Conf]
  30. W. Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:738-743 [Conf]
  31. Le Yan, Lin Zhong, Niraj K. Jha
    User-perceived latency driven voltage scaling for interactive applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:624-627 [Conf]
  32. Wei Zhang, Niraj K. Jha, Li Shang
    NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:711-716 [Conf]
  33. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Architectures for efficient face authentication in embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:1-6 [Conf]
  34. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:178-183 [Conf]
  35. Abhinav Agrawal, Niraj K. Jha
    Synthesis of Reversible Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1384-1385 [Conf]
  36. Bharat P. Dave, Niraj K. Jha
    CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:118-124 [Conf]
  37. Robert P. Dick, Niraj K. Jha
    MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:263-270 [Conf]
  38. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Energy Estimation for Extensible Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10682-10687 [Conf]
  39. Pallav Gupta, Niraj K. Jha
    An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:974-979 [Conf]
  40. Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
    Test generation for combinational quantum cellular automata (QCA) circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:311-316 [Conf]
  41. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:848-854 [Conf]
  42. Jiong Luo, Li-Shiuan Peh, Niraj K. Jha
    Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11150-11151 [Conf]
  43. Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
    Satisfiability-based framework for enabling side-channel attacks on cryptographic software. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:18-23 [Conf]
  44. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    Software Architectural Transformations: A New Approach to Low Energy Embedded Software. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11046-11051 [Conf]
  45. Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
    Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:904-909 [Conf]
  46. Niraj K. Jha
    Nanotechnology in the Service of Embedded and Ubiquitous Computing. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:1- [Conf]
  47. Sandeep Bhatia, Niraj K. Jha
    Genesis: A Behavioral Synthesis System for Hierarchical Testability. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:272-276 [Conf]
  48. Bharat P. Dave, Niraj K. Jha
    COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded System Architectures for Low Overhead Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    FTCS, 1997, pp:339-348 [Conf]
  49. Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller
    Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:280-287 [Conf]
  50. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:336-345 [Conf]
  51. Bapiraju Vinnakota, Niraj K. Jha
    Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:504-511 [Conf]
  52. Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha
    A comprehensive high-level synthesis system for control-flow intensive behaviors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:11-14 [Conf]
  53. Rui Zhang, Niraj K. Jha
    Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:8-13 [Conf]
  54. Jiong Luo, Niraj K. Jha
    Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:679-692 [Conf]
  55. Li Shang, Li-Shiuan Peh, Niraj K. Jha
    Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:91-102 [Conf]
  56. Robert P. Dick, Niraj K. Jha
    MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:522-529 [Conf]
  57. Robert P. Dick, Niraj K. Jha
    CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:62-67 [Conf]
  58. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    A design for testability technique for RTL circuits using control/data flow extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:329-336 [Conf]
  59. Pallav Gupta, Lin Zhong, Niraj K. Jha
    A High-level Interconnect Power Model for Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:551-559 [Conf]
  60. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    High-level synthesis of distributed logic-memory architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:564-571 [Conf]
  61. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:46-53 [Conf]
  62. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    High-level synthesis using computation-unit integrated memories. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:783-790 [Conf]
  63. Niraj K. Jha
    Low Power System Scheduling and Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:259-263 [Conf]
  64. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Memory binding for performance optimization of control-flow intensive behaviors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:482-488 [Conf]
  65. Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
    Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:244-250 [Conf]
  66. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Transforming control-flow intensive designs to facilitate power management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:657-664 [Conf]
  67. Tien-Chien Lee, Wayne Wolf, Niraj K. Jha
    Behavioral synthesis for easy testability in data path scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:616-619 [Conf]
  68. Jiong Luo, Niraj K. Jha
    Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:357-364 [Conf]
  69. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    Register-transfer level estimation techniques for switching activity and power consumption. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:158-165 [Conf]
  70. Anand Raghunathan, Niraj K. Jha
    An iterative improvement algorithm for low power data path synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:597-602 [Conf]
  71. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:577-584 [Conf]
  72. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    A framework for testing core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:385-390 [Conf]
  73. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Synthesis of custom processors based on extensible platforms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:641-648 [Conf]
  74. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A Scalable Application-Specific Processor Synthesis Methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:283-290 [Conf]
  75. Le Yan, Jiong Luo, Niraj K. Jha
    Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:30-38 [Conf]
  76. Lin Zhong, Niraj K. Jha
    Interconnect-aware high-level synthesis for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:110-117 [Conf]
  77. Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Power estimation for cycle-accurate functional descriptions of hardware. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:668-675 [Conf]
  78. Sandeep Bhatia, Niraj K. Jha
    Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:151-154 [Conf]
  79. Sandeep Bhatia, Niraj K. Jha
    Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:91-96 [Conf]
  80. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:173-179 [Conf]
  81. Pallav Gupta, Rui Zhang, Niraj K. Jha
    An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:540-543 [Conf]
  82. Niraj K. Jha, Sying-Jyan Wang
    Design and Synthesis of Self-Checking VLSI Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:578-581 [Conf]
  83. Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka
    Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:369-372 [Conf]
  84. Kamal S. Khouri, Niraj K. Jha
    Leakage Power Analysis and Reduction during Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:561-564 [Conf]
  85. Tien-Chien Lee, Wayne Wolf, Niraj K. Jha, John M. Acken
    Behavioral Synthesis for Easy Testability in Data Path Allocation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:29-32 [Conf]
  86. Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
    Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:187-193 [Conf]
  87. Anand Raghunathan, Niraj K. Jha
    Behavioral Synthesis for low Power. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:318-322 [Conf]
  88. Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
    A Technique for Identifying RTL and Gate-Level Correspondences. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:591-0 [Conf]
  89. Li Shang, Niraj K. Jha
    High-Level Power Modeling of CPLDs and FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:46-53 [Conf]
  90. Santhanam Srinivasan, Niraj K. Jha
    Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:592-595 [Conf]
  91. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    Embedded Operating System Energy Analysis and Macro-Modeling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:515-520 [Conf]
  92. Wei Zhang, Niraj K. Jha
    ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:281-288 [Conf]
  93. Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha
    Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:391-394 [Conf]
  94. Ramesh K. Sitaraman, Niraj K. Jha
    Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessors Systems. [Citation Graph (0, 0)][DBLP]
    Fault-Tolerant Computing Systems, 1991, pp:396-406 [Conf]
  95. Santhanam Srinivasan, Niraj K. Jha
    Task Allocation for Safety and Reliability in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1995, pp:206-213 [Conf]
  96. Shalini Yajnik, Niraj K. Jha
    Design of Algorithm-Based Fault Tolerant Systems With In-System Checks. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:246-253 [Conf]
  97. Li Shang, Li-Shiuan Peh, Niraj K. Jha
    PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:98-108 [Conf]
  98. Keith S. Vallerio, Lin Zhong, Niraj K. Jha
    Energy-Efficient Graphical User Interface Design. [Citation Graph (0, 0)][DBLP]
    International Conference on Wireless Networks, 2004, pp:959-962 [Conf]
  99. Shalini Yajnik, Niraj K. Jha
    Design and Analysis of Fault-Detecting and Fault-Locating Schedules for Computation DAGs. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:348-351 [Conf]
  100. Anand Raghunathan, Niraj K. Jha
    An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1069-1073 [Conf]
  101. Shalini Yajnik, Niraj K. Jha
    Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:333-336 [Conf]
  102. Shalini Yajnik, Niraj K. Jha
    Synthesis of Fault Tolerant Architectures for Molecular Dynamics. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:247-250 [Conf]
  103. Keith S. Vallerio, Niraj K. Jha
    Task graph transformation to aid system synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:695-698 [Conf]
  104. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Active Learning Driven Data Acquisition for Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ISCC, 2006, pp:929-934 [Conf]
  105. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Fast high-level power estimation for control-flow intensive design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:299-304 [Conf]
  106. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Analyzing the energy consumption of security protocols. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:30-35 [Conf]
  107. Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
    Controller re-specification to minimize switching activity in controller/data path circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:301-304 [Conf]
  108. Niraj K. Jha
    Detecting Multiple Faults in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:514-519 [Conf]
  109. Indradeep Ghosh, Niraj K. Jha, Sujit Dey
    A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:50-59 [Conf]
  110. Tien-Chien Lee, Niraj K. Jha, Wayne Wolf
    A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:744-753 [Conf]
  111. Srivaths Ravi, Niraj K. Jha
    Fast test generation for circuits with RTL and gate-level views. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1068-1077 [Conf]
  112. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    : Reducing test application time in high-level test generation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:829-838 [Conf]
  113. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO: regular expression based high-level testability analysis and optimization. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:331-340 [Conf]
  114. Yunsi Fei, Lin Zhong, Niraj K. Jha
    An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2004, pp:306-317 [Conf]
  115. Le Yan, Lin Zhong, Niraj K. Jha
    Towards a Responsive, Yet Power-ef.cient, Operating System: A Holistic Approach. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2005, pp:249-257 [Conf]
  116. Lin Zhong, Mike Sinclair, Niraj K. Jha
    A personal-area network of low-power wireless interfacing devices for handhelds: system and hardware design. [Citation Graph (0, 0)][DBLP]
    Mobile HCI, 2005, pp:251-254 [Conf]
  117. Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha
    Thermal Modeling, Characterization and Management of On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:67-78 [Conf]
  118. Lin Zhong, Niraj K. Jha
    Energy efficiency of handheld computer interfaces: limits, characterization and practice. [Citation Graph (0, 0)][DBLP]
    MobiSys, 2005, pp:247-260 [Conf]
  119. Li Shang, Robert P. Dick, Niraj K. Jha
    An Economics-based Power-aware Protocol for Computation Distribution in Mobile Ad-Hoc Networks. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2002, pp:339-344 [Conf]
  120. Sandeep Bhatia, Niraj K. Jha
    Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:275-280 [Conf]
  121. Bharat P. Dave, Niraj K. Jha
    COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:347-354 [Conf]
  122. Robert P. Dick, Niraj K. Jha
    COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:114-0 [Conf]
  123. Yunsi Fei, Niraj K. Jha
    Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:274-281 [Conf]
  124. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:261-266 [Conf]
  125. Kamal S. Khouri, Niraj K. Jha
    Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:523-529 [Conf]
  126. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    A Power Management Methodology for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:24-19 [Conf]
  127. Loganathan Lingappan, Niraj K. Jha
    Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:431-436 [Conf]
  128. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
    Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:65-70 [Conf]
  129. Jiong Luo, Niraj K. Jha
    Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:719-0 [Conf]
  130. Jiong Luo, Niraj K. Jha
    Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:369-375 [Conf]
  131. Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:171-176 [Conf]
  132. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
    Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:299-304 [Conf]
  133. Srivaths Ravi, Niraj K. Jha
    Synthesis of System-on-a-chip for Testability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:149-156 [Conf]
  134. Li Shang, Niraj K. Jha
    Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:345-0 [Conf]
  135. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:551-556 [Conf]
  136. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:473-476 [Conf]
  137. Keith S. Vallerio, Niraj K. Jha
    Task Graph Extraction for Embedded System Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:480-0 [Conf]
  138. Rui Zhang, Pallav Gupta, Niraj K. Jha
    Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:229-234 [Conf]
  139. Rui Zhang, Niraj K. Jha
    State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:317-322 [Conf]
  140. Lin Zhong, Niraj K. Jha
    Dynamic Power Optimization of Interactive Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1041-1047 [Conf]
  141. Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey
    High-level Synthesis of Multi-process Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:467-473 [Conf]
  142. Weidong Wang, Anand Raghunathan, Niraj K. Jha
    Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:267-0 [Conf]
  143. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Embedded Software Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:711-718 [Conf]
  144. Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha
    Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:504-512 [Conf]
  145. J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard
    Hardware-Software Co-Design for Test: It's the Last Straw! [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:506-507 [Conf]
  146. Loganathan Lingappan, Niraj K. Jha
    Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:418-423 [Conf]
  147. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:398-406 [Conf]
  148. Li Shang, Li-Shiuan Peh, Niraj K. Jha
    Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
  149. Indradeep Ghosh, Niraj K. Jha
    High-level test synthesis: a survey. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:79-99 [Journal]
  150. Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha
    Temperature-Aware On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:130-139 [Journal]
  151. Steven W. Burns, Niraj K. Jha
    A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:490-495 [Journal]
  152. Bharat P. Dave, Niraj K. Jha
    COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:4, pp:417-441 [Journal]
  153. Niraj K. Jha
    Multiple Stuck-Open Fault Detection in CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:4, pp:426-432 [Journal]
  154. Niraj K. Jha
    Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:2, pp:179-189 [Journal]
  155. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:9, pp:865-885 [Journal]
  156. Ramesh K. Sitaraman, Niraj K. Jha
    Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:7, pp:780-793 [Journal]
  157. Bapiraju Vinnakota, Niraj K. Jha
    Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:8, pp:924-937 [Journal]
  158. Sying-Jyan Wang, Niraj K. Jha
    Algorithm-Based Fault Tolerance for FFT Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:7, pp:849-854 [Journal]
  159. Sandeep Bhatia, Niraj K. Jha
    Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:228-243 [Journal]
  160. Bharat P. Dave, Niraj K. Jha
    COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:900-919 [Journal]
  161. Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi
    Controller-based power management for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1496-1508 [Journal]
  162. Konstantinos I. Diamantaras, Niraj K. Jha
    A new transition count method for testing of logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:407-410 [Journal]
  163. Robert P. Dick, Niraj K. Jha
    COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:2-16 [Journal]
  164. Robert P. Dick, Niraj K. Jha
    MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:920-935 [Journal]
  165. Robert P. Dick, Niraj K. Jha
    Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1527-1527 [Journal]
  166. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Analysis of power dissipation in embedded systems using real-time operating systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:615-627 [Journal]
  167. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A hybrid energy-estimation technique for extensible processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:652-664 [Journal]
  168. Indradeep Ghosh, Sujit Dey, Niraj K. Jha
    A fast and low-cost testing technique for core-based system-chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:863-877 [Journal]
  169. Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
    A BIST scheme for RTL circuits based on symbolic testabilityanalysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:111-128 [Journal]
  170. Indradeep Ghosh, Niraj K. Jha, Sujit Dey
    A low overhead design for testability and test generation technique for core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1661-1676 [Journal]
  171. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1001-1014 [Journal]
  172. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    A design-for-testability technique for register-transfer level circuits using control/data flow extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:706-723 [Journal]
  173. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Hierarchical test generation and design for testability methods for ASPPs and ASIPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:357-370 [Journal]
  174. Niraj K. Jha
    Testing for multiple faults in domino-CMOS logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:109-116 [Journal]
  175. Niraj K. Jha
    Separable codes for detecting unidirectional errors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:5, pp:571-574 [Journal]
  176. Niraj K. Jha, Jacob A. Abraham
    Design of Testable CMOS Logic Circuits Under Arbitrary Delays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:264-269 [Journal]
  177. Niraj K. Jha
    Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:3, pp:332-336 [Journal]
  178. Niraj K. Jha
    Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:136-143 [Journal]
  179. Pallav Gupta, Abhinav Agrawal, Niraj K. Jha
    An Algorithm for Synthesis of Reversible Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2317-2330 [Journal]
  180. Gopal Gupta, Niraj K. Jha
    A universal test set for CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:5, pp:590-597 [Journal]
  181. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Generation of distributed logic-memory architectures through high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1694-1711 [Journal]
  182. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Use of Computation-Unit Integrated Memories in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1969-1989 [Journal]
  183. Niraj K. Jha
    A totally self-checking checker for Borden's code. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:731-736 [Journal]
  184. Niraj K. Jha, Abha Ahuja
    Easily testable nonrestoring and restoring gate-level cellular array dividers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:114-123 [Journal]
  185. Niraj K. Jha, Sying-Jyan Wang
    Design and synthesis of self-checking VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:878-887 [Journal]
  186. Kamal S. Khouri, Niraj K. Jha
    Clock selection for performance optimization of control-flowintensive behaviors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:158-165 [Journal]
  187. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    High-level synthesis of low-power control-flow intensive circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1715-1729 [Journal]
  188. Ganesh Lakshminarayana, Niraj K. Jha
    High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:265-281 [Journal]
  189. Ganesh Lakshminarayana, Niraj K. Jha
    FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1577-1594 [Journal]
  190. Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
    Wavesched: a novel scheduling technique for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:505-523 [Journal]
  191. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:308-324 [Journal]
  192. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-case computation: a high-level energy and performance optimization technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:33-49 [Journal]
  193. Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
    Design of robustly testable combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1036-1048 [Journal]
  194. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
    Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2193-2206 [Journal]
  195. Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
    Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:544-557 [Journal]
  196. Jiong Luo, Lin Zhong, Yunsi Fei, Niraj K. Jha
    Register binding-based RTL power management for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1175-1183 [Journal]
  197. Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1514-1521 [Journal]
  198. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    Register transfer level power optimization with emphasis on glitch analysis and reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1114-1131 [Journal]
  199. Anand Raghunathan, Niraj K. Jha
    SCALP: an iterative-improvement-based low-power data path synthesis system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1260-1277 [Journal]
  200. Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
    Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1414-1425 [Journal]
  201. Srivaths Ravi, Niraj K. Jha
    Test synthesis of systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1211-1217 [Journal]
  202. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:894-906 [Journal]
  203. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    Testing of core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:426-439 [Journal]
  204. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    High-level test compaction techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:827-841 [Journal]
  205. Li Shang, Li-Shiuan Peh, Niraj K. Jha
    PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:92-110 [Journal]
  206. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Custom-instruction synthesis for extensible-processor platforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:216-228 [Journal]
  207. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Application-specific heterogeneous multiprocessor synthesis using extensible processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1589-1602 [Journal]
  208. Andres R. Takach, Niraj K. Jha
    Easily testable gate-level and DCVS multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:932-942 [Journal]
  209. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    A simulation framework for energy-consumption analysis of OS-driven embedded applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1284-1294 [Journal]
  210. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    High-level energy macromodeling of embedded software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1037-1050 [Journal]
  211. Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Resource budgeting for Multiprocess High-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1010-1019 [Journal]
  212. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input space-adaptive optimization for embedded-software synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1677-1693 [Journal]
  213. Le Yan, Jiong Luo, Niraj K. Jha
    Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1030-1041 [Journal]
  214. Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
    Threshold network synthesis and optimization and its application to nanotechnologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:107-118 [Journal]
  215. Lin Zhong, Niraj K. Jha
    Interconnect-aware low-power high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:336-351 [Journal]
  216. Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    RTL-Aware Cycle-Accurate Functional Power Estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2103-2117 [Journal]
  217. Tat Kee Tan, Anand Raghunathan, Niraj K. Jha
    Energy macromodeling of embedded operating systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:231-254 [Journal]
  218. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Mob. Comput., 2006, v:5, n:2, pp:128-143 [Journal]
  219. Li Shang, Robert P. Dick, Niraj K. Jha
    DESP: A Distributed Economics-Based Subcontracting Protocol for Computation Distribution in Power-Aware Mobile Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Mob. Comput., 2004, v:3, n:1, pp:33-45 [Journal]
  220. Keith S. Vallerio, Lin Zhong, Niraj K. Jha
    Energy-Efficient Graphical User Interface Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Mob. Comput., 2006, v:5, n:7, pp:846-859 [Journal]
  221. Lin Zhong, Niraj K. Jha
    Dynamic Power Optimization Targeting User Delays in Interactive Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Mob. Comput., 2006, v:5, n:11, pp:1473-1488 [Journal]
  222. Jennifer Rexford, Niraj K. Jha
    Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:6, pp:649-653 [Journal]
  223. S. Srinivasan, Niraj K. Jha
    Safety and Reliability Driven Task Allocation in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:3, pp:238-251 [Journal]
  224. Bapiraju Vinnakota, Niraj K. Jha
    Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:8, pp:864-874 [Journal]
  225. Bapiraju Vinnakota, Niraj K. Jha
    Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:10, pp:1099-1106 [Journal]
  226. Shalini Yajnik, Niraj K. Jha
    Analysis and Randomized Design of Algorithm-Based Fault Tolerant Multiprocessor Systems Under an Extended Model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:7, pp:757-768 [Journal]
  227. Shalini Yajnik, Niraj K. Jha
    Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:2, pp:137-153 [Journal]
  228. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Memory binding for performance optimization of control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:513-524 [Journal]
  229. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input space adaptive design: a high-level methodology for optimizing energy and performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:590-602 [Journal]
  230. Wei Zhang, Li Shang, Niraj K. Jha
    NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:300-305 [Conf]
  231. Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Energy and execution time analysis of a software-based trusted platform module. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1128-1133 [Conf]
  232. Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha
    Express virtual channels: towards the ideal interconnection fabric. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:150-161 [Conf]
  233. Niraj K. Jha
    Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:249-261 [Journal]
  234. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A Scalable Synthesis Methodology for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1175-1188 [Journal]
  235. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1295-1308 [Journal]
  236. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Architectural Support for Run-Time Validation of Program Data Properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:546-559 [Journal]
  237. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:296-308 [Journal]
  238. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
    Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:605-609 [Journal]
  239. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:699-710 [Journal]
  240. Jiong Luo, Niraj K. Jha, Li-Shiuan Peh
    Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:427-437 [Journal]
  241. Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
    Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:465-470 [Journal]
  242. Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
    A Test Generation Framework for Quantum Cellular Automata Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:24-36 [Journal]
  243. Loganathan Lingappan, Niraj K. Jha
    Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:518-530 [Journal]
  244. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1191-1204 [Journal]
  245. Sandeep Bhatia, Niraj K. Jha
    Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:608-619 [Journal]
  246. Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
    COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:92-104 [Journal]
  247. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Power management in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:7-15 [Journal]
  248. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO: regular expression-based register-transfer level testability analysis and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:824-832 [Journal]
  249. Kamal S. Khouri, Niraj K. Jha
    Leakage power analysis and reduction during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:876-885 [Journal]
  250. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    High-level macro-modeling and estimation techniques for switching activity and power consumption. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:538-557 [Journal]

  251. A Secure User Interface for Web Applications Running Under an Untrusted Operating System. [Citation Graph (, )][DBLP]


  252. An architecture for secure software defined radio. [Citation Graph (, )][DBLP]


  253. Low-power FinFET circuit synthesis using surface orientation optimization. [Citation Graph (, )][DBLP]


  254. Dynamic Binary Instrumentation-Based Framework for Malware Defense. [Citation Graph (, )][DBLP]


  255. Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems. [Citation Graph (, )][DBLP]


  256. Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. [Citation Graph (, )][DBLP]


  257. In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects. [Citation Graph (, )][DBLP]


  258. CMOS logic design with independent-gate FinFETs. [Citation Graph (, )][DBLP]


  259. A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. [Citation Graph (, )][DBLP]


  260. A system-level perspective for efficient NoC design. [Citation Graph (, )][DBLP]


  261. GARNET: A detailed on-chip network model inside a full-system simulator. [Citation Graph (, )][DBLP]


  262. Die-level leakage power analysis of FinFET circuits considering process variations. [Citation Graph (, )][DBLP]


  263. Token flow control. [Citation Graph (, )][DBLP]


  264. In-network coherence filtering: snoopy coherence without broadcasts. [Citation Graph (, )][DBLP]


  265. Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. [Citation Graph (, )][DBLP]


  266. Variability-Tolerant Register-Transfer Level Synthesis. [Citation Graph (, )][DBLP]


  267. Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. [Citation Graph (, )][DBLP]


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