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Li-C. Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tao Feng, Li-C. Wang, Kwang-Ting Cheng
    Improved symbolic simulation by functional-space decomposition. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:634-639 [Conf]
  2. Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang
    Module placement with boundary constraints using the sequence-pair representation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:515-520 [Conf]
  3. Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
    Jitter spectral extraction for multi-gigahertz signal. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:298-303 [Conf]
  4. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
    Efficient reachability checking using sequential SAT. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:418-423 [Conf]
  5. Kai Yang, Kwang-Ting Cheng, Li-C. Wang
    TranGen: a SAT-based ATPG for path-oriented transition faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:92-97 [Conf]
  6. Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
    Collaboration between Industry and Academia in Test Research. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:17-0 [Conf]
  7. Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer
    On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:151-0 [Conf]
  8. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
    Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:668-673 [Conf]
  9. Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
    Refined statistical static timing analysis through. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:149-154 [Conf]
  10. Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
    A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:436-441 [Conf]
  11. Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
    False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:566-569 [Conf]
  12. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Enhancing test efficiency for delay fault testing using multiple-clocked schemes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:371-374 [Conf]
  13. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
    An efficient finite-domain constraint solver for circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:212-217 [Conf]
  14. Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy
    Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:534-537 [Conf]
  15. Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir
    On path-based learning and its applications in delay test and diagnosis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:492-497 [Conf]
  16. Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin
    Improved Symoblic Simulation by Dynamic Funtional Space Partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:42-49 [Conf]
  17. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
    Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10328-10335 [Conf]
  18. Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen
    An Efficient Sequential SAT Solver With Improved Search Strategies. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1102-1107 [Conf]
  19. Feng Lu, Li-C. Wang, Kwang-Ting Cheng, Ric C.-Y. Huang
    A Circuit SAT Solver With Signal Correlation Guided Learning. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10892-10897 [Conf]
  20. Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
    Pattern Selection for Testing of Deep Sub-Micron Timing Defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:160- [Conf]
  21. Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
    Random Jitter Extraction Technique in a Multi-Gigahertz Signal. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:286-291 [Conf]
  22. Li-C. Wang
    Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:692-695 [Conf]
  23. Li-C. Wang, Magdy S. Abadir, Jing Zeng
    Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:273-277 [Conf]
  24. Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer
    Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:177-185 [Conf]
  25. Leonard Lee, Sean Wu, Charles H.-P. Wen, Li-C. Wang
    On Generating Tests to Cover Diverse Worst-Case Timing Corners. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:415-426 [Conf]
  26. Arun Chandra, Li-C. Wang, Magdy S. Abadir
    Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:362-367 [Conf]
  27. Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Hillel Miller, Magdy S. Abadir
    Extracting a Simplified View of Design Functionality Based on Vector Simulation. [Citation Graph (0, 0)][DBLP]
    Haifa Verification Conference, 2006, pp:34-49 [Conf]
  28. Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng
    A path-based methodology for post-silicon timing validation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:713-720 [Conf]
  29. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng
    On theoretical and practical considerations of path selection for delay fault testing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:94-100 [Conf]
  30. Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu
    Static statistical timing analysis for latch-based pipeline designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:468-472 [Conf]
  31. Leonard Lee, Li-C. Wang
    On bounding the delay of a critical path. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:81-88 [Conf]
  32. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    A Better ATPG Algorithm and Its Design Principles. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:248-253 [Conf]
  33. Magdy S. Abadir, Li-C. Wang
    Verification and Validation of Complex Digital Systems: An Industrial Perspective. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:11-12 [Conf]
  34. Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang
    On Structural vs. Functional Testing for Delay Faults. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:438-441 [Conf]
  35. Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
    Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:930-939 [Conf]
  36. Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
    Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1031-1037 [Conf]
  37. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak
    Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:339-348 [Conf]
  38. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:407-416 [Conf]
  39. Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
    Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:203-212 [Conf]
  40. Li-C. Wang, Magdy S. Abadir
    A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:954-963 [Conf]
  41. Li-C. Wang, Magdy S. Abadir
    Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:830-838 [Conf]
  42. Li-C. Wang, Magdy S. Abadir, Juhong Zhu
    On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:398-406 [Conf]
  43. Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
    Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1041-1050 [Conf]
  44. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    On Efficiently and Reliably Achieving Low Defective Part Levels. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:616-625 [Conf]
  45. Li-C. Wang, M. Ray Mercer, Thomas W. Williams
    Using Target Faults To Detect Non-Tartget Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:629-638 [Conf]
  46. Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham
    On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:31-37 [Conf]
  47. Charles H.-P. Wen, Li-C. Wang
    Simulation Data Mining for Functional Test Pattern Justification. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:76-83 [Conf]
  48. Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham
    On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:103-109 [Conf]
  49. Albert G. Greenberg, Boris D. Lubachevsky, Li-C. Wang
    Experience in Massively Parallel Discrete Event Simulation. [Citation Graph (0, 0)][DBLP]
    SPAA, 1993, pp:193-202 [Conf]
  50. Magdy S. Abadir, Juhong Zhu, Li-C. Wang
    Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:252-259 [Conf]
  51. Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer
    REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:268-274 [Conf]
  52. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou
    Diagnosis of Delay Defects Using Statistical Timing Models. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:339-344 [Conf]
  53. Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
    Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:153-160 [Conf]
  54. Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak
    On Silicon-Based Speed Path Identification. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:35-41 [Conf]
  55. Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
    A Scalable On-Chip Jitter Extraction Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:267-272 [Conf]
  56. Li-C. Wang, Magdy S. Abadir, Jing Zeng
    On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:260-265 [Conf]
  57. Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams
    On the decline of testing efficiency as fault coverage approaches 100%. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:74-83 [Conf]
  58. Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen
    On A Software-Based Self-Test Methodology and Its Application. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:107-113 [Conf]
  59. Magdy S. Abadir, Li-C. Wang
    Guest Editors' Introduction: The Verification and Test of Complex Digital ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:80-82 [Journal]
  60. Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang
    Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:6-7 [Journal]
  61. Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang
    Defect-Oriented Testing and Defective-Part-Level Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:1, pp:31-41 [Journal]
  62. T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
    New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:241-247 [Journal]
  63. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
    Safety Property Verification Using Sequential SAT and Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:132-143 [Journal]
  64. Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna
    A Signal Correlation Guided Circuit-SAT Solver. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2004, v:10, n:12, pp:1629-1654 [Journal]
  65. Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng
    Simulation-Based Functional Test Generation for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:11, pp:1335-1343 [Journal]
  66. Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang
    Multilevel circuit clustering for delay minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1073-1085 [Journal]
  67. Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng
    Critical path selection for delay fault testing based upon a statistical timing model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1550-1565 [Journal]
  68. Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin
    Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:4, pp:627-650 [Journal]
  69. Li-C. Wang, Magdy S. Abadir, Jing Zeng
    On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:524-532 [Journal]
  70. Li-C. Wang, Pouria Bastani, Magdy S. Abadir
    Design-Silicon Timing Correlation A Data Mining Perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:384-389 [Conf]

  71. Path selection for monitoring unexpected systematic timing effects. [Citation Graph (, )][DBLP]


  72. Functional test selection based on unsupervised support vector analysis. [Citation Graph (, )][DBLP]


  73. Statistical diagnosis of unmodeled systematic timing effects. [Citation Graph (, )][DBLP]


  74. Speedpath prediction based on learning from a small set of examples. [Citation Graph (, )][DBLP]


  75. Speedpath analysis based on hypothesis pruning and ranking. [Citation Graph (, )][DBLP]


  76. Predicting variability in nanoscale lithography processes. [Citation Graph (, )][DBLP]


  77. Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. [Citation Graph (, )][DBLP]


  78. Data Learning Techniques for Functional/System Fmax Prediction. [Citation Graph (, )][DBLP]


  79. An incremental learning framework for estimating signal controllability in unit-level verification. [Citation Graph (, )][DBLP]


  80. Simulation-based functional test justification using a decision-digram-based Boolean data miner. [Citation Graph (, )][DBLP]


  81. On evaluating speed path detection of structural tests. [Citation Graph (, )][DBLP]


  82. Analog behavioral modeling flow using statistical learning method. [Citation Graph (, )][DBLP]


  83. A non-parametric approach to behavioral device modeling. [Citation Graph (, )][DBLP]


  84. A Survey of Hybrid Techniques for Functional Verification. [Citation Graph (, )][DBLP]


  85. Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. [Citation Graph (, )][DBLP]


  86. Linking Statistical Learning to Diagnosis. [Citation Graph (, )][DBLP]


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