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Kwang-Ting Cheng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tao Feng, Li-C. Wang, Kwang-Ting Cheng
    Improved symbolic simulation by functional-space decomposition. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:634-639 [Conf]
  2. Uwe Gläser, Kwang-Ting Cheng
    Logic optimization by an improved sequential redundancy addition and removal techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Jiun-Lang Huang, Kwang-Ting Cheng
    A sigma-delta modulation based BIST scheme for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:605-612 [Conf]
  4. Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho
    A Hybrid Power Model for RTL Power Estimation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:551-556 [Conf]
  5. Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng
    Constraint extraction for pseudo-functional scan-based delay testing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:166-171 [Conf]
  6. Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu
    Performance sensitivity analysis using statistical method and its applications to delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:587-592 [Conf]
  7. Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
    Jitter spectral extraction for multi-gigahertz signal. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:298-303 [Conf]
  8. Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
    Generation of shorter sequences for high resolution error diagnosis using sequential SAT. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:25-29 [Conf]
  9. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
    Efficient reachability checking using sequential SAT. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:418-423 [Conf]
  10. Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal
    A testability metric for path delay faults and its application. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:593-598 [Conf]
  11. Kai Yang, Kwang-Ting Cheng
    Efficient identification of multi-cycle false path. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:360-365 [Conf]
  12. Kai Yang, Kwang-Ting Cheng, Li-C. Wang
    TranGen: a SAT-based ATPG for path-oriented transition faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:92-97 [Conf]
  13. Vishwani D. Agrawal, Kwang-Ting Cheng
    Testing in the Fourth Dimension. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:2-0 [Conf]
  14. Kwang-Ting Cheng
    Built-In Self Test for Analog and Mixed-Signal Designs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:197-198 [Conf]
  15. Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
    Collaboration between Industry and Academia in Test Research. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:17-0 [Conf]
  16. Melvin A. Breuer, Kwang-Ting Cheng
    Challenges for the Academic Test Community. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:4-0 [Conf]
  17. Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu
    On-chip Analog Response Extraction with 1-Bit ? - Modulators. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:49-0 [Conf]
  18. Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng
    A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:62-67 [Conf]
  19. Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu
    An FPGA-based re-configurable functional tester for memory chips. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:51-57 [Conf]
  20. Hisashi Kondo, Kwang-Ting Cheng
    An Efficient Compact Test Generator for IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:177-182 [Conf]
  21. Kingshy Goh, Edward Y. Chang, Kwang-Ting Cheng
    SVM Binary Classifier Ensembles for Image Classification. [Citation Graph (0, 0)][DBLP]
    CIKM, 2001, pp:395-402 [Conf]
  22. Qiang Zhu, Mei-Chen Yeh, Kwang-Ting Cheng, Shai Avidan
    Fast Human Detection Using a Cascade of Histograms of Oriented Gradients. [Citation Graph (0, 0)][DBLP]
    CVPR (2), 2006, pp:1491-1498 [Conf]
  23. Vishwani D. Agrawal, Kwang-Ting Cheng
    Test Function Specification in Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:235-240 [Conf]
  24. Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal
    Contest: A Concurrent Test Generator for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:84-89 [Conf]
  25. Ying-Tsai Chang, Kwang-Ting Cheng
    Self-referential verification of gate-level implementations of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:311-316 [Conf]
  26. Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
    Layout Driven Logic Synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:308-313 [Conf]
  27. Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng
    A Test Synthesis Approach to Reducing BALLAST DFT Overhead. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:466-471 [Conf]
  28. Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
    An Efficient Algorithm for Local Don't Care Sets Calculation. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:663-667 [Conf]
  29. Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wen-Long Wei
    Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1083-1088 [Conf]
  30. Kwang-Ting Cheng
    On Removing Redundancy in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:164-169 [Conf]
  31. Kwang-Ting Cheng, Vishwani D. Agrawal
    An Entropy Measure for the Complexity of Multi-Output Boolean Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:302-305 [Conf]
  32. Kwang-Ting Cheng, Hsi-Chuan Chen
    Generation of High Quality Non-Robust Tests for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:365-369 [Conf]
  33. David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska
    A New Hybrid Methodology for Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:439-444 [Conf]
  34. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:80-86 [Conf]
  35. Kwang-Ting Cheng, A. S. Krishnakumar
    Automatic Functional Test Generation Using the Extended Finite State Machine Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:86-91 [Conf]
  36. Kwang-Ting Cheng, Hi-Keung Tony Ma
    On the Over-Specification Problem in Sequential ATPG Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:16-21 [Conf]
  37. Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy
    Test challenges for deep sub-micron technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:142-149 [Conf]
  38. Chung-Yang Huang, Kwang-Ting Cheng
    Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:118-123 [Conf]
  39. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
    Error Correction Based on Verification Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:258-261 [Conf]
  40. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee
    Compact Vector Generation for Accurate Power Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:161-164 [Conf]
  41. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu
    Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:632-637 [Conf]
  42. Yi-Min Jiang, Kwang-Ting Cheng
    Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:760-765 [Conf]
  43. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
    Post-Layout Logic Restructuring for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:662-665 [Conf]
  44. A. S. Krishnakumar, Kwang-Ting Cheng
    On the Computation of the Set of Reachable States of Hybrid Models. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:615-621 [Conf]
  45. Angela Krstic, Kwang-Ting Cheng
    Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:383-388 [Conf]
  46. Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
    Embedded software-based self-testing for SoC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:355-360 [Conf]
  47. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
    Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:668-673 [Conf]
  48. Wei-Cheng Lai, Kwang-Ting Cheng
    Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:59-64 [Conf]
  49. Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
    A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:436-441 [Conf]
  50. Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
    Logic Synthesis for Engineering Change. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:647-652 [Conf]
  51. Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
    Test Point Insertion: Scan Paths through Combinational Logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:268-273 [Conf]
  52. Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
    Fast Statistical Timing Analysis By Probabilistic Event Propagation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:661-666 [Conf]
  53. Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
    False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:566-569 [Conf]
  54. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Enhancing test efficiency for delay fault testing using multiple-clocked schemes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:371-374 [Conf]
  55. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
    Structural search for RTL with predicate learning. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:451-456 [Conf]
  56. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
    An efficient finite-domain constraint solver for circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:212-217 [Conf]
  57. Irith Pomeranz, Kwang-Ting Cheng
    State Assignment Using Input/Output Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:573-577 [Conf]
  58. Uwe Sparmann, D. Luxenburger, Kwang-Ting Cheng, Sudhakar M. Reddy
    Fast Identification of Robust Dependent Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:119-125 [Conf]
  59. Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
    Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:748-753 [Conf]
  60. Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
    A Hybrid Algorithm for Test Point Selection for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:478-483 [Conf]
  61. Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir
    On path-based learning and its applications in delay test and diagnosis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:492-497 [Conf]
  62. Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee
    Functional Scan Chain Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:278-0 [Conf]
  63. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng
    Coverage loss by using space compactors in presence of unknown values. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1053-1054 [Conf]
  64. Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin
    Improved Symoblic Simulation by Dynamic Funtional Space Partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:42-49 [Conf]
  65. Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
    A BIST Scheme for On-Chip ADC and DAC Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:216-220 [Conf]
  66. Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng
    Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:666-671 [Conf]
  67. Yi-Min Jiang, Kwang-Ting Cheng
    Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:698-0 [Conf]
  68. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
    Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10328-10335 [Conf]
  69. Yung-Chieh Lin, Kwang-Ting Cheng
    Multiple-fault diagnosis based on single-fault activation and single-output observation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:424-429 [Conf]
  70. Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen
    An Efficient Sequential SAT Solver With Improved Search Strategies. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1102-1107 [Conf]
  71. Feng Lu, Li-C. Wang, Kwang-Ting Cheng, Ric C.-Y. Huang
    A Circuit SAT Solver With Signal Correlation Guided Learning. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10892-10897 [Conf]
  72. Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
    Pattern Selection for Testing of Deep Sub-Micron Timing Defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:160- [Conf]
  73. Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
    Random Jitter Extraction Technique in a Multi-Gigahertz Signal. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:286-291 [Conf]
  74. Kai Yang, Kwang-Ting Cheng
    Timing-reasoning-based delay fault diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:418-423 [Conf]
  75. Qiang Zhu, Kwang-Ting Cheng, Ching-Tung Wu, Yi-Leh Wu
    Adaptive Learning of an Accurate Skin-Color Model. [Citation Graph (0, 0)][DBLP]
    FGR, 2004, pp:37-42 [Conf]
  76. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
    On Verifying the Correctness of Retimed Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:277-0 [Conf]
  77. Ying-Tsai Chang, Kwang-Ting Cheng
    Induction-Based Gate-Level Verification of Multipliers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:190-0 [Conf]
  78. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
    Response shaper: a novel technique to enhance unknown tolerance for output response compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:80-87 [Conf]
  79. Kwang-Ting Cheng
    An ATPG-Based Approach to Sequential Logic Optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:372-375 [Conf]
  80. Kwang-Ting Cheng
    Test generation for delay faults in non-scan and partial scan sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:554-559 [Conf]
  81. Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai
    Fault emulation: a new approach to fault grading. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:681-686 [Conf]
  82. Kwang-Ting Cheng, Jing-Yang Jou
    A Single-State-Transition Fault Model for Sequential Machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:226-229 [Conf]
  83. Luis Entrena, Kwang-Ting Cheng
    Sequential logic optimization by redundancy addition and removal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:310-315 [Conf]
  84. Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng
    SATORI - A Fast Sequential SAT Engine for Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:320-325 [Conf]
  85. Jing-Yang Jou, Kwang-Ting Cheng
    Timing-Driven Partial Scan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:404-407 [Conf]
  86. Hisashi Kondo, Kwang-Ting Cheng
    Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:228-232 [Conf]
  87. Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng
    A path-based methodology for post-silicon timing validation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:713-720 [Conf]
  88. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:493-496 [Conf]
  89. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng
    On theoretical and practical considerations of path selection for delay fault testing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:94-100 [Conf]
  90. Chen-Yang Pan, Kwang-Ting Cheng
    Pseudo-random testing and signature analysis for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:102-107 [Conf]
  91. Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta
    A comprehensive fault macromodel for opamps. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:344-348 [Conf]
  92. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer
    RTL SAT simplification by Boolean and interval arithmetic reasoning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:297-302 [Conf]
  93. Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu
    Static statistical timing analysis for latch-based pipeline designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:468-472 [Conf]
  94. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng
    Timing Optimization with Testability Considerations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:460-463 [Conf]
  95. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
    ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:147-152 [Conf]
  96. Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
    Accurate Diagnosis of Multiple Faults. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:153-156 [Conf]
  97. Qiang Zhu, Shai Avidan, Kwang-Ting Cheng
    Learning a Sparse, Corner-Based Representation for Time-varying Background Modeling. [Citation Graph (0, 0)][DBLP]
    ICCV, 2005, pp:678-685 [Conf]
  98. Beitao Li, Wei-Cheng Lai, Edward Y. Chang, Kwang-Ting Cheng
    Mining Image Features for Efficient Query Processing. [Citation Graph (0, 0)][DBLP]
    ICDM, 2001, pp:353-360 [Conf]
  99. Qiang Zhu, Kwang-Ting Cheng, Ching-Tung Wu
    A unified adaptive approach to accurate skin detection. [Citation Graph (0, 0)][DBLP]
    ICIP, 2004, pp:1189-1192 [Conf]
  100. Ching-Tung Wu, Kwang-Ting Cheng, Qiang Zhu, Yi-Leh Wu
    Using visual features for anti-spam filtering. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2005, pp:509-512 [Conf]
  101. Qiang Zhu, Kwang-Ting Cheng, HongJiang Zhang
    SSD tracking using dynamic template and log-polar transformation. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:723-726 [Conf]
  102. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee
    A novel methodology for transistor-level power estimation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:67-72 [Conf]
  103. Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng
    Estimation of maximum power supply noise for deep sub-micron designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:233-238 [Conf]
  104. Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng
    VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:156-161 [Conf]
  105. Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng
    LIBRA - a library-independent framework for post-layout performance optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:135-140 [Conf]
  106. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Dynamic Timing Analysis Considering Power Supply Noise Effects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:137-144 [Conf]
  107. Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng
    HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:307-312 [Conf]
  108. Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang
    On Structural vs. Functional Testing for Delay Faults. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:438-441 [Conf]
  109. Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, R. Tutundjian
    Fault Simulation in a Pipelined Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:727-734 [Conf]
  110. Kwang-Ting Cheng
    The Confluence of Manufacturing Test and Design Validation. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1293- [Conf]
  111. Kwang-Ting Cheng
    Transition Fault Simulation for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:723-731 [Conf]
  112. Kwang-Ting Cheng
    National Science Foundation Workshop on Future Research Directions in Testing of Electronic Circuits and Systems: executive summary of workshop report. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1157-0 [Conf]
  113. Kwang-Ting Cheng, Hsi-Chuan Chen
    Delay Testing for Non-Robust Untestable Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:954-961 [Conf]
  114. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:403-410 [Conf]
  115. Kwang-Ting Cheng, Chih-Jen Lin
    Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:506-514 [Conf]
  116. Jiun-Lang Huang, Kwang-Ting Cheng
    Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1021-1030 [Conf]
  117. Jiun-Lang Huang, Kwang-Ting Cheng
    Analog Fault Diagnosis for Unpowered Circuit Boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:640-648 [Conf]
  118. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng
    Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:974-981 [Conf]
  119. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser
    An ATPG-Based Framework for Verifying Sequential Equivalence. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:865-874 [Conf]
  120. Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng
    Static property checking using ATPG vs. BDD techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:309-316 [Conf]
  121. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Delay testing considering power supply noise effects. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:181-190 [Conf]
  122. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
    Identification and Test Generation for Primitive Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:423-432 [Conf]
  123. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
    Design for Primitive Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:436-445 [Conf]
  124. Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng
    Delay testing considering crosstalk-induced effects. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:558-567 [Conf]
  125. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak
    Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:339-348 [Conf]
  126. Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
    Test program synthesis for path delay faults in microprocessor cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1080-1089 [Conf]
  127. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:407-416 [Conf]
  128. Chen-Yang Pan, Kwang-Ting Cheng
    Fault Macromodeling for Analog/Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:913-922 [Conf]
  129. Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
    Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:203-212 [Conf]
  130. Subrata Roy, Gokhan Guner, Kwang-Ting Cheng
    Efficient test mode selection and insertion for RTL-BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:263-272 [Conf]
  131. Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng
    An almost full-scan BIST solution-higher fault coverage and shorter test application time. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1065-0 [Conf]
  132. Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
    Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1041-1050 [Conf]
  133. Edward Y. Chang, Kwang-Ting Cheng, Wei-Cheng Lai, Ching-Tung Wu, Chengwei Chang, Yi-Leh Wu
    PBIR: perception-based image retrieval-a system that can quickly capture subjective image query concepts. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2001, pp:611-614 [Conf]
  134. Wei-Cheng Lai, Chengwei Chang, Edward Y. Chang, Kwang-Ting Cheng, Michael Crandell
    PBIR-MM: multimodal image retrieval and annotation. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2002, pp:421-422 [Conf]
  135. Qiang Zhu, Ching-Tung Wu, Kwang-Ting Cheng, Yi-Leh Wu
    An adaptive skin model and its application to objectionable image filtering. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2004, pp:56-63 [Conf]
  136. Wei-Cheng Lai, Edward Y. Chang, Kwang-Ting Cheng
    Hybrid Learning Schemes for Multimedia Information Retrieval. [Citation Graph (0, 0)][DBLP]
    IEEE Pacific Rim Conference on Multimedia, 2002, pp:556-563 [Conf]
  137. Yi-Leh Wu, Edward Y. Chang, Kwang-Ting Cheng, Chengwei Chang, Chen-Cha Hsu, Wei-Cheng Lai, Ching-Tung Wu
    MORF: A Distributed Multimodal Information Filtering System. [Citation Graph (0, 0)][DBLP]
    IEEE Pacific Rim Conference on Multimedia, 2002, pp:279-286 [Conf]
  138. Kwang-Ting Cheng
    Partial scan designs without using a separate scan clock. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:277-282 [Conf]
  139. Jiun-Lang Huang, Kwang-Ting Cheng
    An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:380-387 [Conf]
  140. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
    Incremental logic rectification. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:143-149 [Conf]
  141. Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng
    A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:198-203 [Conf]
  142. Jiun-Lang Huang, Chen-Yang Pan, Kwang-Ting Cheng
    Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:220-225 [Conf]
  143. Angela Krstic, Kwang-Ting Cheng
    Generation of high quality tests for functional sensitizable paths. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:374-379 [Conf]
  144. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou
    Diagnosis of Delay Defects Using Statistical Timing Models. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:339-344 [Conf]
  145. Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
    On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:15-22 [Conf]
  146. Madhu K. Iyer, Kwang-Ting Cheng
    Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:139-144 [Conf]
  147. Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
    Pseudo-Functional Scan-based BIST for Delay Fault. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:229-234 [Conf]
  148. Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee
    Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:97-104 [Conf]
  149. Chen-Yang Pan, Kwang-Ting Cheng
    Implicit functional testing for analog circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:489-494 [Conf]
  150. Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
    A Scalable On-Chip Jitter Extraction Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:267-272 [Conf]
  151. Kaushik Roy, T. M. Mak, Kwang-Ting Cheng
    Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:313-318 [Conf]
  152. Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen
    On A Software-Based Self-Test Methodology and Its Application. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:107-113 [Conf]
  153. Kwang-Ting Cheng, Angela Krstic
    Current Directions in Automatic Test-Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:11, pp:58-64 [Journal]
  154. Kwang-Ting Cheng
    New beginnings, continued success. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:1, pp:5-6 [Journal]
  155. Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
    Embedded Software-Based Self-Test for Programmable Core-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:18-27 [Journal]
  156. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang
    Safety Property Verification Using Sequential SAT and Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:132-143 [Journal]
  157. Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng
    Testable Path Delay Fault Cover for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:673-686 [Journal]
  158. Kwang-Ting Cheng, Vishwani D. Agrawal
    A Partial Scan Method for Sequential Circuits with Feedback. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:544-549 [Journal]
  159. Kwang-Ting Cheng, Vishwani D. Agrawal
    Initializability Consideration in Sequential Machine Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:3, pp:374-379 [Journal]
  160. Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh
    A Simulation-Based Method for Generating Tests for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:12, pp:1456-1463 [Journal]
  161. Kwang-Ting Cheng, Angela Krstic, Hsi-Chuan Chen
    Generation of High Quality Tests for Robustly Untestable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:12, pp:1379-1392 [Journal]
  162. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer
    AQUILA: An Equivalence Checking System for Large Sequential Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:5, pp:443-464 [Journal]
  163. Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng
    Simulation-Based Functional Test Generation for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:11, pp:1335-1343 [Journal]
  164. Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal
    A directed search method for test generation using a concurrent simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:131-138 [Journal]
  165. Ying-Tsai Chang, Kwang-Ting Cheng
    Self-referential verification for gate-level implementations of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1102-1112 [Journal]
  166. Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
    Postlayout logic restructuring using alternative wires. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:587-596 [Journal]
  167. Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
    Perturb and simplify: multilevel Boolean network optimizer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1494-1504 [Journal]
  168. Kwang-Ting Cheng
    Redundancy removal for sequential circuits without reset states. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:13-24 [Journal]
  169. Kwang-Ting Cheng
    Transition fault testing for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1971-1983 [Journal]
  170. Kwang-Ting Cheng, Hsi-Chuan Chen
    Classification and identification of nonrobust untestable path delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:845-853 [Journal]
  171. David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska
    A hybrid methodology for switching activities estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:357-366 [Journal]
  172. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    Delay-fault test generation and synthesis for testability under a standard scan design methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1217-1231 [Journal]
  173. Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai
    Fault emulation: A new methodology for fault grading. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1487-1495 [Journal]
  174. Kwang-Ting Cheng, Jing-Yang Jou
    A functional fault model for sequential machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1065-1073 [Journal]
  175. Kwang-Ting Cheng, Hi-Keung Tony Ma
    On the over-specification problem in sequential ATPG algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1599-1604 [Journal]
  176. Luis Entrena-Arrontes, Kwang-Ting Cheng
    Combinational and sequential logic optimization by redundancy addition and removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:7, pp:909-916 [Journal]
  177. Chung-Yang Huang, Kwang-Ting Cheng
    Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:381-391 [Journal]
  178. Shi-Yu Huang, Kwang-Ting Cheng
    ErrorTracer: design error diagnosis based on fault simulation techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1341-1352 [Journal]
  179. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
    AutoFix: a hybrid tool for automatic logic rectification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1376-1384 [Journal]
  180. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
    Primitive delay faults: identification, testing, and design for testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:669-684 [Journal]
  181. Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:416-425 [Journal]
  182. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:756-769 [Journal]
  183. Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
    Pseudofunctional testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1535-1546 [Journal]
  184. Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
    Test-point insertion: scan paths through functional logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:838-851 [Journal]
  185. Chen-Yang Pan, Kwang-Ting Cheng
    Pseudorandom testing for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1173-1185 [Journal]
  186. Irith Pomeranz, Kwang-Ting Cheng
    STOIC: state assignment based on output/input functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1123-1131 [Journal]
  187. Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
    On improving test quality of scan-based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:928-938 [Journal]
  188. Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng
    Critical path selection for delay fault testing based upon a statistical timing model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1550-1565 [Journal]
  189. Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin
    Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:4, pp:627-650 [Journal]
  190. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
    Verifying sequential equivalence using ATPG techniques. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:2, pp:244-275 [Journal]
  191. Kwang-Ting Cheng
    Gate-level test generation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:4, pp:405-442 [Journal]
  192. Kwang-Ting Cheng, A. S. Krishnakumar
    Automatic generation of functional vectors using the extended finite state machine model. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:1, pp:57-79 [Journal]
  193. Tsung-Ching Huang, Huai-Yuan Tseng, Chen-Pang Kung, Kwang-Ting Cheng
    Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan Driver. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:966-969 [Conf]
  194. Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng
    A framework for system reliability analysis considering both system error tolerance and component test quality. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1581-1586 [Conf]
  195. Dongwoo Hong, Shadi Saberi, Kwang-Ting Cheng, C. Patrick Yue
    A two-tone test method for continuous-time adaptive equalizers. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1283-1288 [Conf]
  196. Qiang Zhu, Mei-Chen Yeh, Kwang-Ting Cheng
    Multimodal fusion using learned text concepts for image categorization. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2006, pp:211-220 [Conf]
  197. Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
    Efficient test-point selection for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:667-676 [Journal]
  198. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Estimation for maximum instantaneous current through supply lines for CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:61-73 [Journal]
  199. Yi-Min Jiang, Kwang-Ting Cheng
    Vector generation for power supply noise estimation and verification of deep submicron designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:329-340 [Journal]

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