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Görschwin Fey: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Görschwin Fey, Rolf Drechsler
    Improving simulation-based verification by means of formal methods. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:640-643 [Conf]
  2. Junhao Shi, Görschwin Fey, Rolf Drechsler
    Bridging fault testability of BDD circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:188-191 [Conf]
  3. Junhao Shi, Görschwin Fey, Rolf Drechsler
    BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:290-293 [Conf]
  4. Görschwin Fey, Daniel Große, Rolf Drechsler
    Avoiding false negatives in formal verification for protocol-driven blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1225-1226 [Conf]
  5. Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
    On the relation between simulation-based and SAT-based diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1139-1144 [Conf]
  6. Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
    Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:162-167 [Conf]
  7. Daniel Tille, Görschwin Fey, Rolf Drechsler
    Instance Generation for SAT-based ATPG. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:153-156 [Conf]
  8. Görschwin Fey, Junhao Shi, Rolf Drechsler
    BDD Circuit Optimization for Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:168-172 [Conf]
  9. Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
    Disjoint Sum of Product Minimization by Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2004, pp:198-207 [Conf]
  10. Rolf Drechsler, Junhao Shi, Görschwin Fey
    MuTaTe: an efficient design for testability technique for multiplexor based circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:80-83 [Conf]
  11. Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler
    Utilizing don't care states in SAT-based bounded sequential problems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:264-269 [Conf]
  12. Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
    Automatic Fault Localization for Property Checking. [Citation Graph (0, 0)][DBLP]
    Haifa Verification Conference, 2006, pp:50-64 [Conf]
  13. Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski
    Algorithms for Taylor Expansion Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:235-240 [Conf]
  14. Görschwin Fey, Sebastian Kinder, Rolf Drechsler
    Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:361-366 [Conf]
  15. Görschwin Fey, Junhao Shi, Rolf Drechsler
    Efficiency of Multi-Valued Encoding in SAT-based ATPG. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:25- [Conf]
  16. Daniel Große, Görschwin Fey, Rolf Drechsler
    Modeling Multi-Valued Circuits in SystemC. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:281-286 [Conf]
  17. Sebastian Kinder, Görschwin Fey, Rolf Drechsler
    Controlling the Memory During Manipulation of Word-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:250-255 [Conf]
  18. Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
    PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:212-217 [Conf]
  19. Görschwin Fey, Rolf Drechsler
    Finding Good Counter-Examples to Aid Design Verification. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:51-0 [Conf]
  20. Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
    SyCE: An Integrated Environment for System Design in SystemC. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:258-260 [Conf]
  21. Rolf Drechsler, Görschwin Fey, Sebastian Kinder
    An Integrated Approach for Combining BDD and SAT Provers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:237-242 [Conf]
  22. Görschwin Fey, Tim Warode, Rolf Drechsler
    Reusing Learned Information in SAT-based ATPG. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:69-76 [Conf]
  23. Rolf Drechsler, Junhao Shi, Görschwin Fey
    Synthesis of fully testable circuits from BDDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:440-443 [Journal]
  24. Görschwin Fey, Rolf Drechsler
    Minimizing the number of paths in BDDs: Theory and algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:4-11 [Journal]
  25. Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
    SAT-based ATPG for Path Delay Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3671-3674 [Conf]
  26. Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
    Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:181-187 [Conf]
  27. Rolf Drechsler, Görschwin Fey
    Automatic Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    SFM, 2006, pp:30-55 [Conf]

  28. Computing bounds for fault tolerance using formal techniques. [Citation Graph (, )][DBLP]


  29. Automatic Generation of Complex Properties for Hardware Designs. [Citation Graph (, )][DBLP]


  30. Increasing the accuracy of SAT-based debugging. [Citation Graph (, )][DBLP]


  31. On the Construction of Small Fully Testable Circuits with Low Depth. [Citation Graph (, )][DBLP]


  32. Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. [Citation Graph (, )][DBLP]


  33. Robustness Check for Multiple Faults Using Formal Techniques. [Citation Graph (, )][DBLP]


  34. Using unsatisfiable cores to debug multiple design errors. [Citation Graph (, )][DBLP]


  35. Experimental Studies on SAT-Based ATPG for Gate Delay Faults. [Citation Graph (, )][DBLP]


  36. Evaluation of Cardinality Constraints on SMT-Based Debugging. [Citation Graph (, )][DBLP]


  37. A Basis for Formal Robustness Checking. [Citation Graph (, )][DBLP]


  38. WoLFram- A Word Level Framework for Formal Verification. [Citation Graph (, )][DBLP]


  39. SWORD: A SAT like prover using word level information. [Citation Graph (, )][DBLP]


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