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Publications of Author

1. Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
   Abstraction and optimization of consistent floorplanning with pillar block constraints. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:19-24 [Conf]
   
2. Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
   Self-reforming routing for stochastic search in VLSI interconnection layout. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:87-92 [Conf]
   
3. Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
   Multi-level placement with circuit schema based clustering in analog IC layouts. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:406-411 [Conf]
   
4. Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
   The oct-touched tile: a new architecture for shape-based routing. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:126-129 [Conf]
   
5. Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
   A device-level placement with multi-directional convex clustering. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2004, pp:196-201 [Conf]
   
6. Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani
   How does partitioning matter for 3D floorplanning? [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2006, pp:73-78 [Conf]
   
7. Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake
   A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2004, pp:489-492 [Conf]
   
8. 
   A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks. [Citation Graph (, )][DBLP]
   
   
9. 
   Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. [Citation Graph (, )][DBLP]
   
   
10. 
    ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. [Citation Graph (, )][DBLP]