The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Hidetoshi Onodera: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru
    A method for linking process-level variability to system performances. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:547-552 [Conf]
  2. Masanori Hashimoto, Hidetoshi Onodera
    Post-layout transistor sizing for power reduction in cell-based design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:359-365 [Conf]
  3. Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
    Timing analysis considering temporal supply voltage fluctuation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1098-1101 [Conf]
  4. Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
    Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:110-111 [Conf]
  5. Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera
    A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:619-622 [Conf]
  6. Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera
    A vector-pipeline DSP for low-rate videophones. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:1-2 [Conf]
  7. Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
    A model-adaptable MOSFET parameter extraction system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  8. Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera
    A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:545-546 [Conf]
  9. Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
    Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:267-268 [Conf]
  10. Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
    Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:723-728 [Conf]
  11. Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera
    Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:9-10 [Conf]
  12. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
    Representative frequency for interconnect R(f)L(f)C extraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:691-696 [Conf]
  13. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
    Return path selection for loop RL extraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1078-1081 [Conf]
  14. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
    Interconnect RL extraction at a single representative frequency. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:515-520 [Conf]
  15. Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera
    A dynamically phase adjusting PLL with a variable delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:275-280 [Conf]
  16. Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera
    An SoC architecture and its design methodology using unifunctional heterogeneous processor array. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:737-742 [Conf]
  17. Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
    A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:446-451 [Conf]
  18. Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru
    Branch-and-Bound Placement for Building Block Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:433-439 [Conf]
  19. Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
    Timing and Power Optimization by Gate Sizing Considering False Paths. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:154-0 [Conf]
  20. Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
    An iterative gate sizing approach with accurate delay evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:422-427 [Conf]
  21. Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
    Equivalent Waveform Propagation for Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:169-175 [Conf]
  22. Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera
    Timing analysis considering spatial power/ground level variation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:814-820 [Conf]
  23. Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru
    Proposal of a timing model for CMOS logic gates driving a CRC load. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:537-544 [Conf]
  24. Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru
    Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:100-103 [Conf]
  25. Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
    A Statistical Gate-Delay Model Considering Intra-Gate Variability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:908-913 [Conf]
  26. Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera
    Crosstalk Noise Estimation for Generic RC Trees. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:110-117 [Conf]
  27. Ken-ichi Okada, Hiroaki Hoshino, Hidetoshi Onodera
    Modelling and optimization of on-chip spiral inductor in S-parameter domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:153-156 [Conf]
  28. Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
    Statistical modeling of gate-delay variation with consideration of intra-gate variability. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:513-516 [Conf]
  29. Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera
    RTL/ISS co-modeling methodology for embedded processor using SystemC. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:305-308 [Conf]
  30. Kazutoshi Kobayashi, Hidetoshi Onodera
    ST: PERL package for simulation and test environment. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:89-92 [Conf]
  31. Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
    A power optimization method considering glitch reduction by gate sizing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:221-226 [Conf]
  32. Masanori Hashimoto, Hidetoshi Onodera
    A performance optimization method by gate sizing using statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:111-116 [Conf]
  33. Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera
    Crosstalk noise optimization by post-layout transistor sizing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:126-130 [Conf]
  34. Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
    Capturing crosstalk-induced waveform for accurate static timing analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:18-23 [Conf]
  35. Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
    Effects of on-chip inductance on power distribution grid. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:63-69 [Conf]
  36. Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera
    Automatic Generation of Standard Cell Library in VDSM Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:36-41 [Conf]
  37. Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera
    Statistical Analysis of Clock Skew Variation in H-Tree Structure. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:402-407 [Conf]
  38. Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera
    Experimental Study on Cell-Base High-Performance Datapath Design. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:283-287 [Conf]
  39. Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
    Equivalent waveform propagation for static timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:498-508 [Journal]
  40. Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
    Model-adaptable MOSFET parameter-extraction method using an intermediate model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:400-405 [Journal]
  41. K. Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Y. Sugihara, Hidetoshi Onodera
    A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  42. Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
    Worst-case delay analysis considering the variability of transistors and interconnects. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:35-42 [Conf]

  43. Dependable VLSI: device, design and architecture: how should they cooperate? [Citation Graph (, )][DBLP]


  44. A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. [Citation Graph (, )][DBLP]


  45. A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. [Citation Graph (, )][DBLP]


  46. Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. [Citation Graph (, )][DBLP]


  47. Statistical gate delay model for Multiple Input Switching. [Citation Graph (, )][DBLP]


  48. Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. [Citation Graph (, )][DBLP]


  49. Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. [Citation Graph (, )][DBLP]


  50. A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. [Citation Graph (, )][DBLP]


  51. Erect of regularity-enhanced layout on printability and circuit performance of standard cells. [Citation Graph (, )][DBLP]


Search in 0.006secs, Finished in 0.008secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002