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Hidetoshi Onodera:
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Publications of Author
- Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru
A method for linking process-level variability to system performances. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:547-552 [Conf]
- Masanori Hashimoto, Hidetoshi Onodera
Post-layout transistor sizing for power reduction in cell-based design. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:359-365 [Conf]
- Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
Timing analysis considering temporal supply voltage fluctuation. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:1098-1101 [Conf]
- Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:110-111 [Conf]
- Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:619-622 [Conf]
- Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera
A vector-pipeline DSP for low-rate videophones. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:1-2 [Conf]
- Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
A model-adaptable MOSFET parameter extraction system. [Citation Graph (0, 0)][DBLP] ASP-DAC, 1995, pp:- [Conf]
- Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:545-546 [Conf]
- Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:267-268 [Conf]
- Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:723-728 [Conf]
- Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:9-10 [Conf]
- Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
Representative frequency for interconnect R(f)L(f)C extraction. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:691-696 [Conf]
- Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
Return path selection for loop RL extraction. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:1078-1081 [Conf]
- Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
Interconnect RL extraction at a single representative frequency. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:515-520 [Conf]
- Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera
A dynamically phase adjusting PLL with a variable delay. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:275-280 [Conf]
- Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera
An SoC architecture and its design methodology using unifunctional heterogeneous processor array. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:737-742 [Conf]
- Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. [Citation Graph (0, 0)][DBLP] DAC, 1999, pp:446-451 [Conf]
- Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru
Branch-and-Bound Placement for Building Block Layout. [Citation Graph (0, 0)][DBLP] DAC, 1991, pp:433-439 [Conf]
- Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
Timing and Power Optimization by Gate Sizing Considering False Paths. [Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1996, pp:154-0 [Conf]
- Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
An iterative gate sizing approach with accurate delay evaluation. [Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:422-427 [Conf]
- Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
Equivalent Waveform Propagation for Static Timing Analysis. [Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:169-175 [Conf]
- Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera
Timing analysis considering spatial power/ground level variation. [Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:814-820 [Conf]
- Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru
Proposal of a timing model for CMOS logic gates driving a CRC load. [Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:537-544 [Conf]
- Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. [Citation Graph (0, 0)][DBLP] ICCAD, 1993, pp:100-103 [Conf]
- Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
A Statistical Gate-Delay Model Considering Intra-Gate Variability. [Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:908-913 [Conf]
- Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera
Crosstalk Noise Estimation for Generic RC Trees. [Citation Graph (0, 0)][DBLP] ICCD, 2001, pp:110-117 [Conf]
- Ken-ichi Okada, Hiroaki Hoshino, Hidetoshi Onodera
Modelling and optimization of on-chip spiral inductor in S-parameter domain. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:153-156 [Conf]
- Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
Statistical modeling of gate-delay variation with consideration of intra-gate variability. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:513-516 [Conf]
- Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera
RTL/ISS co-modeling methodology for embedded processor using SystemC. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:305-308 [Conf]
- Kazutoshi Kobayashi, Hidetoshi Onodera
ST: PERL package for simulation and test environment. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2001, pp:89-92 [Conf]
- Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
A power optimization method considering glitch reduction by gate sizing. [Citation Graph (0, 0)][DBLP] ISLPED, 1998, pp:221-226 [Conf]
- Masanori Hashimoto, Hidetoshi Onodera
A performance optimization method by gate sizing using statistical static timing analysis. [Citation Graph (0, 0)][DBLP] ISPD, 2000, pp:111-116 [Conf]
- Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera
Crosstalk noise optimization by post-layout transistor sizing. [Citation Graph (0, 0)][DBLP] ISPD, 2002, pp:126-130 [Conf]
- Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
Capturing crosstalk-induced waveform for accurate static timing analysis. [Citation Graph (0, 0)][DBLP] ISPD, 2003, pp:18-23 [Conf]
- Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
Effects of on-chip inductance on power distribution grid. [Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:63-69 [Conf]
- Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera
Automatic Generation of Standard Cell Library in VDSM Technologies. [Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:36-41 [Conf]
- Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera
Statistical Analysis of Clock Skew Variation in H-Tree Structure. [Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:402-407 [Conf]
- Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera
Experimental Study on Cell-Base High-Performance Datapath Design. [Citation Graph (0, 0)][DBLP] IWLS, 2002, pp:283-287 [Conf]
- Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
Equivalent waveform propagation for static timing analysis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:498-508 [Journal]
- Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
Model-adaptable MOSFET parameter-extraction method using an intermediate model. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:400-405 [Journal]
- K. Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Y. Sugihara, Hidetoshi Onodera
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. [Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-4 [Conf]
- Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
Worst-case delay analysis considering the variability of transistors and interconnects. [Citation Graph (0, 0)][DBLP] ISPD, 2007, pp:35-42 [Conf]
Dependable VLSI: device, design and architecture: how should they cooperate? [Citation Graph (, )][DBLP]
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. [Citation Graph (, )][DBLP]
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. [Citation Graph (, )][DBLP]
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. [Citation Graph (, )][DBLP]
Statistical gate delay model for Multiple Input Switching. [Citation Graph (, )][DBLP]
Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. [Citation Graph (, )][DBLP]
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. [Citation Graph (, )][DBLP]
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. [Citation Graph (, )][DBLP]
Erect of regularity-enhanced layout on printability and circuit performance of standard cells. [Citation Graph (, )][DBLP]
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