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Publications of Author

1. Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru
   A method for linking process-level variability to system performances. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:547-552 [Conf]
   
2. Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
   A model-adaptable MOSFET parameter extraction system. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1995, pp:- [Conf]
   
3. Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru
   A scheduling algorithm for synthesis of bus-partitioned architectures. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1995, pp:- [Conf]
   
4. Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
   A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:446-451 [Conf]
   
5. Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru
   Branch-and-Bound Placement for Building Block Layout. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:433-439 [Conf]
   
6. Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
   Timing and Power Optimization by Gate Sizing Considering False Paths. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1996, pp:154-0 [Conf]
   
7. Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
   An iterative gate sizing approach with accurate delay evaluation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:422-427 [Conf]
   
8. Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru
   Proposal of a timing model for CMOS logic gates driving a CRC load. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:537-544 [Conf]
   
9. Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru
   Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1993, pp:100-103 [Conf]
   
10. M. Ohmura, Hiroto Yasuura, Keikichi Tamaru
    Extraction of Functional Information from Combinatorial Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:176-179 [Conf]
    
11. Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura
    Design of data-path module generators from algorithmic representations. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:183-192 [Conf]
    
12. Vasily G. Moshnyaga, Keikichi Tamaru
    A Memory Efficient Array Architecture for Real-Time Motion Estimation. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:28-32 [Conf]
    
13. Farhad Fuad Islam, Keikichi Tamaru
    An Architecture for Intermediate Area-time Complexity Multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1825-1828 [Conf]
    
14. Kuei-Ming Lu, Keikichi Tamaru
    A New Algorithm for Sorting Problem with Reformed CAM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1045-1048 [Conf]
    
15. Vasily G. Moshnyaga, Keikichi Tamaru
    A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1560-1563 [Conf]
    
16. Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
    A power optimization method considering glitch reduction by gate sizing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:221-226 [Conf]
    
17. Vasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru
    A memory efficient array architecture for real-time motion estimation. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1998, v:29, n:9, pp:13-20 [Journal]
    
18. Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
    Model-adaptable MOSFET parameter-extraction method using an intermediate model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:400-405 [Journal]