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Yasuo Sato: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
    A dynamic test compaction procedure for high-quality path delay testing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:348-353 [Conf]
  2. Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
    Evaluation of the statistical delay quality model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:305-310 [Conf]
  3. Kazumi Hatayama, Michinobu Nakao, Yasuo Sato
    At-Speed Built-in Test for Logic Circuits with Multiple Clocks. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:292-297 [Conf]
  4. Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo
    Test Generation for Multiple-Threshold Gate-Delay Fault Model. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:244-0 [Conf]
  5. Yasuo Sato, M. Sato, K. Tsutsumida, Toyohito Ikeya, M. Kawashima
    A Practical Logic BIST for ASIC Designs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:457- [Conf]
  6. Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato
    An Approach to Improve the Resolution of Defect-Based Diagnosis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:123-0 [Conf]
  7. Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
    Path delay test compaction with process variation tolerance. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:845-850 [Conf]
  8. Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima
    Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:253-258 [Conf]
  9. Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
    Effective Post-BIST Fault Diagnosis for Multiple Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:401-109 [Conf]
  10. Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
    Application of High-Quality Built-In Test to Industrial Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1003-1012 [Conf]
  11. Yasuo Sato, Toyohito Ikeya, Machinobu Nakao, Takaharu Nagumo
    A BIST approach for very deep sub-micron (VDSM) defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:283-291 [Conf]
  12. Yasuo Sato, Msaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto
    An evaluation of defect-oriented test: WELL-controlled low voltage test. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1059-1067 [Conf]
  13. Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura
    A Persistent Diagnostic Technique for Unstable Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:242-249 [Conf]

  14. On estimation of NBTI-Induced delay degradation. [Citation Graph (, )][DBLP]

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