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Isao Shirakawa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Makoto Furuie, Bao-Yu Song, Yukihiro Yoshida, Takao Onoye, Isao Shirakawa
    Layout generation of array cell for NMOS 4-phase dynamic logic (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:529-532 [Conf]
  2. Akira Nagao, Chiyoshi Yoshioka, Takashi Kambe, Isao Shirakawa
    A layout approach to Monolithic Microwave IC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
    A dynamically reconfigurable hardware-based cipher chip. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:11-12 [Conf]
  4. Keisuke Okada, Shun Morikawa, Isao Shirakawa, Sumitaka Takeuchi
    A design of high-performance multiplier for digital video transmission. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  5. Roberto Y. Omaki, Yu Dong, Morgan Hirosuke Miki, Makoto Furuie, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa
    Realtime wavelet video coder based on reduced memory accessing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:15-16 [Conf]
  6. Takao Onoye, Gen Fujita, Hiroyuki Okuhata, Morgan Hirosuke Miki, Isao Shirakawa
    Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:589-594 [Conf]
  7. Hiroshi Uno, Toru Chiba, Keiji Kumatani, Isao Shirakawa
    Synthesis and simulation of digital demodulator for infrared data communication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  8. Atsushi Kosaka, Satoshi Yamaguchi, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa
    SoC design of Ogg Vorbis decoder using embedded processor. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:481-487 [Conf]
  9. Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Y. Meng
    FeRAM Circuit Technology for System on a Chip. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 1999, pp:193-0 [Conf]
  10. Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa
    Interconnect capacitance extraction for system LCD circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:160-163 [Conf]
  11. Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
    On the layering problem of multilayer PWB wiring. [Citation Graph (0, 0)][DBLP]
    Graph Theory and Algorithms, 1980, pp:20-37 [Conf]
  12. Katsuya Nakagawa, Masaru Kawakita, Koji Sato, Mitsuru Minakuchi, Osamu Tsumori, Keitaro Hanada, Toru Chiba, Isao Shirakawa
    OCEAN: Object Communication Environment for Arbitrary Network. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2002, pp:162-168 [Conf]
  13. Kenji Hontani, Takaaki Imanaka, Gen Fujita, Takao Onoye, Isao Shirakawa
    Real-time face object extraction for video phone. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2003, pp:873-876 [Conf]
  14. Yu Dong, Roberto Y. Omaki, Takao Onoye, Isao Shirakawa
    VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  15. Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa
    Evaluation of processor code efficiency for embedded systems. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:229-235 [Conf]
  16. Morgan Hirosuke Miki, Motoki Kimura, Takao Onoye, Isao Shirakawa
    High Performance Java Hardware Engine and Software Kernel for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:109-120 [Conf]
  17. Hitoshi Nishimura, Hiroshi Ohno, Toru Kawata, Isao Shirakawa, Koichi Omura
    LINKS-1: A Parallel Pipelined Multimicrocomputer System for Image Creation [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:387-394 [Conf]
  18. S. Komata, A. Pal, Noriaki Sakamoto, Wataru Kobayashi, Takao Onoye, Isao Shirakawa
    Interactive interface of realtime 3D sound movement for embedded applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:520-523 [Conf]
  19. T. Matsumura, N. Iwanaga, Takao Onoye, Wataru Kobayashi, Isao Shirakawa, Itthichai Arungsrisangchai
    3D sound movement system for embedded applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5345-5348 [Conf]
  20. Takayuki Sagishima, Kozo Kimura, Hiroaki Hirata, Tokuzo Kiyohara, Shigeo Asahara, Takao Onoye, Isao Shirakawa
    Multi-Threaded Processor for Image Generation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:231-234 [Conf]
  21. Masahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa
    A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:185-188 [Conf]
  22. Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe
    Optimal Scheduling for Conditional Recource Sharing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2297-2300 [Conf]
  23. Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
    VLSI architecture of dynamically reconfigurable hardware-based cipher. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:734-737 [Conf]
  24. Morgan Hirosuke Miki, Daisuke Taki, Gen Fujita, Takao Onoye, Isao Shirakawa, T. Fujiwara, T. Kasami
    Recursive maximum likelihood decoder for high-speed satellite communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:572-575 [Conf]
  25. H. Fujishima, Y. Takemoto, T. Yoneda, Takao Onoye, Isao Shirakawa
    Hybrid media-processor core for natural and synthetic video decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:275-278 [Conf]
  26. Yoshihiro Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, K. Onoye, Isao Shirakawa, Toru Chiba
    Error correction block based ARQ protocol for wireless digital video transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:605-608 [Conf]
  27. Yoshihiro Uchida, M. Ise, Takao Onoye, Isao Shirakawa, Itthichai Arungsrisangchai
    VLSI architecture of digital matched filter and prime interleaver for W-CDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:269-272 [Conf]
  28. Morgan Hirosuke Miki, Gen Fujita, Takao Onoye, Isao Shirakawa
    Low-power H.263 video CoDec dedicated to mobile computing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:80-83 [Conf]
  29. Hiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba
    Low power architecture for high speed infrared wireless communication system. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:255-258 [Conf]
  30. Yukihiro Yoshida, Bao-Yu Song, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa
    An object code compression approach to embedded processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:265-268 [Conf]
  31. Akira Nagao, Takashi Kambe, Isao Shirakawa
    A layout approach to monolithic microwave IC. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:65-72 [Conf]
  32. T. Kaya, Isao Shirakawa, Ryusuke Miyamoto, Takao Onoye
    Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:- [Conf]
  33. Kenji Matsumura, Gen Fujita, T. Masaki, Isao Shirakawa, Hiroshi Inada
    A wireless data processing system constructed of SAW-devices and its applications to medical cares. [Citation Graph (0, 0)][DBLP]
    NSIP, 1999, pp:803-805 [Conf]
  34. Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Takashi Kambe
    Optimal layout recycling based on graph theoretic linear programming approach. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:25-34 [Conf]
  35. Shuji Tsukiyama, Isao Shirakawa, Hiroshi Ozaki, Hiromu Ariyoshi
    An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1980, v:27, n:4, pp:619-632 [Journal]
  36. Noriaki Sakamoto, Wataru Kobayashi, Takao Onoye, Isao Shirakawa
    Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:1, pp:55-74 [Journal]
  37. Katsunori Tani, Shuji Tsukiyama, Shoji Shinoda, Isao Shirakawa
    On area-efficient drawings of rectangular duals for VLSI floor-plan. [Citation Graph (0, 0)][DBLP]
    Math. Program., 1991, v:52, n:, pp:29-43 [Journal]
  38. Shuji Tsukiyama, Mikio Ide, Hiromu Ariyoshi, Isao Shirakawa
    A New Algorithm for Generating All the Maximal Independent Sets. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1977, v:6, n:3, pp:505-517 [Journal]
  39. Ikuo Nishioka, Takuji Kurimoto, Seiji Yamamoto, Toru Chiba, Isao Shirakawa, Hiroshi Ozaki
    An Approach to Gate Assignment and Module Placement for Printed Wiring Boards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:8, pp:681-688 [Journal]
  40. Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki
    A Layout System for the Random Logic Portion of an MOS LSI Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:8, pp:572-581 [Journal]
  41. Akira Nagao, Isao Shirakawa, Takashi Kambe
    A layout approach to monolithic microwave IC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1262-1272 [Journal]
  42. Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Itthichai Arungsrisangchai, Hiromitsu Takahashi
    Automatic layout recycling based on layout description and linear programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:959-967 [Journal]
  43. Isao Shirakawa, Shin Futagami
    A Rerouting Scheme for Single-Layer Printed Wiring Boards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:4, pp:267-271 [Journal]
  44. Shuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa
    A New Global Router for Gate Array LSIsi. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:4, pp:313-321 [Journal]
  45. Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
    On the Layering Problem of Multilayer PWB Wiring. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:1, pp:30-38 [Journal]
  46. Hiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba
    ASK digital demodulation scheme for noise immune infrared data communication. [Citation Graph (0, 0)][DBLP]
    Wireless Networks, 1997, v:3, n:2, pp:121-129 [Journal]

  47. Embedded implementation of acoustic field enhancement for stereo headphones. [Citation Graph (, )][DBLP]


  48. Realtime face object extraction algorithm for video phone. [Citation Graph (, )][DBLP]


  49. Parasitic capacitance modeling for multilevel interconnects. [Citation Graph (, )][DBLP]


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