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Title:
Author:
Adnan Aziz: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Malay K. Ganai, Adnan Aziz
    Improved SAT-based Bounded Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:729-734 [Conf]
  2. I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
    Integrated power supply planning and floorplanning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:589-594 [Conf]
  3. Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz
    Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists. [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:72-83 [Conf]
  4. Jason Baumgartner, Anson Tripp, Adnan Aziz, Vigyan Singhal, Flemming Andersen
    An Abstraction Algorithm for the Verification of Generalized C-Slow Designs. [Citation Graph (0, 0)][DBLP]
    CAV, 2000, pp:5-19 [Conf]
  5. Adnan Aziz, Felice Balarin, Robert K. Brayton, M. D. DiBenedetto, Alexander Saldanha
    Supervisory Control of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:279-292 [Conf]
  6. Adnan Aziz, Vigyan Singhal, Felice Balarin
    It Usually Works: The Temporal Logic of Stochastic Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:155-165 [Conf]
  7. Adnan Aziz, Thomas R. Shiple, Vigyan Singhal
    Formula-Dependent Equivalence for Compositional CTL Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:324-337 [Conf]
  8. Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton
    Verifying Continuous Time Markov Chains. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:269-276 [Conf]
  9. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS: A System for Verification and Synthesis. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:428-432 [Conf]
  10. Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
    BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:244-255 [Conf]
  11. Jun Yuan, Jian Shen, Jacob A. Abraham, Adnan Aziz
    On Combining Formal and Informal Verification. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:376-387 [Conf]
  12. Hari Mony, Jason Baumgartner, Adnan Aziz
    Exploiting Constraints in Transformation-Based Verification. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:269-284 [Conf]
  13. Adnan Aziz, Serdar Tasiran, Robert K. Brayton
    BDD Variable Ordering for Interacting Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:283-288 [Conf]
  14. Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    HSIS: A BDD-Based Environment for Formal Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:454-459 [Conf]
  15. Adnan Aziz, James H. Kukula, Thomas R. Shiple
    Hybrid Verification Using Saturated Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:615-618 [Conf]
  16. Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann
    Enhancing Simulation with BDDs and ATPG. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:385-390 [Conf]
  17. Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz
    Hybrid Techniques for Fast Functional Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:664-667 [Conf]
  18. Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal
    Optimizing Designs Containing Black Boxes. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:113-116 [Conf]
  19. Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne Wolf
    Synthesizing interconnect-efficient low density parity check codes. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:488-491 [Conf]
  20. Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
    Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:96-99 [Conf]
  21. Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
    Constraint synthesis for environment modeling in functional verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:296-299 [Conf]
  22. I-Min Liu, Adnan Aziz, D. F. Wong
    Meeting Delay Constraints in DSM by Minimal Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:436-440 [Conf]
  23. Praveen Yalagandula, Adnan Aziz, Vigyan Singhal
    Automatic Lighthouse Generation for Directed State Space Search. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:237-242 [Conf]
  24. James H. Kukula, Thomas R. Shiple, Adnan Aziz
    Techniques for Implicit State Enumeration of EFSMs. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:469-482 [Conf]
  25. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:248-256 [Conf]
  26. Malay K. Ganai, Adnan Aziz
    Rarity based guided state space search. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:97-102 [Conf]
  27. Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Equivalences for Fair Kripke Structures. [Citation Graph (0, 0)][DBLP]
    ICALP, 1994, pp:364-375 [Conf]
  28. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential synthesis using S1S. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:612-617 [Conf]
  29. Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli
    Sequential optimisation without state space exploration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:208-215 [Conf]
  30. Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton
    Multi-level synthesis for safe replaceability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:442-449 [Conf]
  31. Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
    Simplifying Boolean constraint solving for random simulation-vector generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:123-127 [Conf]
  32. Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin
    A Framework for Constrained Functional Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:142-145 [Conf]
  33. Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz
    Modeling design constraints and biasing in simulation using BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:584-590 [Conf]
  34. Fadi A. Zaraket, Jason Baumgartner, Adnan Aziz
    Scalable compositional minimization via static analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1060-1067 [Conf]
  35. Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton
    Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:255-261 [Conf]
  36. I-Min Liu, Adnan Aziz
    Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:209-214 [Conf]
  37. I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
    An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:210-215 [Conf]
  38. Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid
    Sequential Circuits for Relational Analysis. [Citation Graph (0, 0)][DBLP]
    ICSE, 2007, pp:13-22 [Conf]
  39. Amit Prakash, Adnan Aziz, Vijaya Ramachandran
    Randomized Parallel Schedulers for Switch-Memory-Switch Routers: Analysis and Numerical Studies. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2004, pp:- [Conf]
  40. Sadia Sharif, Adnan Aziz, Amit Prakash
    An O(log2N) parallel algorithm for output queuing. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2002, pp:- [Conf]
  41. I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong
    Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:33-38 [Conf]
  42. Hai Zhou, Adnan Aziz
    Buffer minimization in pass transistor logic. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:105-110 [Conf]
  43. Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud
    Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:873-878 [Conf]
  44. Jun Yuan, Kurt Shultz, John Havlicek, Ken Albin, Adnan Aziz
    A Method for Synthesizing Boolean Constrains. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:351-353 [Conf]
  45. Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz
    A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:97-102 [Conf]
  46. Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
    Simplifying Constraint Solving in Random Simulation Generation. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:185-190 [Conf]
  47. Adnan Aziz, Amit Prakash, Vijaya Ramachandran
    A near optimal scheduler for switch-memory-switch routers. [Citation Graph (0, 0)][DBLP]
    SPAA, 2003, pp:343-352 [Conf]
  48. Malay K. Ganai, Adnan Aziz
    Improved SAT-Based Bounded Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:729-734 [Conf]
  49. Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns
    Performance Driven Synthesis for Pass-Transistor Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:372-377 [Conf]
  50. Srivatsan Srinivasan, Parminder Singh Chhabra, Praveen Kumar Jaini, Adnan Aziz, Lizy Kurian John
    Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:288-293 [Conf]
  51. Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Formula-Dependent Equivalence for Compositional CTL Model Checking. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:21, n:2, pp:193-224 [Journal]
  52. Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz
    An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:23, n:1, pp:39-65 [Journal]
  53. Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
    BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:22, n:3, pp:205-224 [Journal]
  54. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential synthesis using S1S. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1149-1162 [Journal]
  55. Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan
    Efficient control state-space search. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:332-336 [Journal]
  56. Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz
    A high-performance architecture and BDD-based synthesis methodology for packet classification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:698-709 [Journal]
  57. Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
    Theory of safe replacements for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:249-265 [Journal]
  58. Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin
    Simplifying Boolean constraint solving for random simulation-vector generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:412-420 [Journal]
  59. Hai Zhou, Adnan Aziz
    Buffer minimization in pass transistor logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:693-697 [Journal]
  60. Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
    Simultaneous routing and buffer insertion with restrictions onbuffer locations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:819-824 [Journal]
  61. Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton
    Model-checking continous-time Markov chains. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Log., 2000, v:1, n:1, pp:162-170 [Journal]
  62. Tai-Hung Liu, Adnan Aziz, Vigyan Singhal
    Optimizing designs containing black boxes. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:591-601 [Journal]
  63. Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton
    Sequential optimization in the absence of global reset. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:222-251 [Journal]
  64. Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud
    Implementing DSP Algorithms with On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:307-316 [Conf]
  65. Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky
    Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  66. TuneFPGA: post-silicon tuning of dual-Vdd FPGAs. [Citation Graph (, )][DBLP]


  67. Exploiting power-up delay for sequential optimization. [Citation Graph (, )][DBLP]


  68. Optimal Constraint-Preserving Netlist Simplification. [Citation Graph (, )][DBLP]


  69. Global Optimization of Compositional Systems. [Citation Graph (, )][DBLP]


  70. A Middle Ground between CAMs and DAGs for High-Speed Packet Classification. [Citation Graph (, )][DBLP]


  71. Multicast Scheduling for Switches with Multiple Input-Queues. [Citation Graph (, )][DBLP]


  72. Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. [Citation Graph (, )][DBLP]


  73. Adaptive SRAM memory for low power and high yield. [Citation Graph (, )][DBLP]


  74. TuneLogic: Post-silicon tuning of dual-Vdd designs. [Citation Graph (, )][DBLP]


  75. Sequential circuits for program analysis. [Citation Graph (, )][DBLP]


  76. The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. [Citation Graph (, )][DBLP]


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