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Publications of Author

1. Youxin Gao, D. F. Wong
   A fast and accurate delay estimation method for buffered interconnects. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:533-538 [Conf]
   
2. Youxin Gao, D. F. Wong
   Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1999, pp:217-220 [Conf]
   
3. Youxin Gao, D. F. Wong
   Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:512-0 [Conf]
   
4. Youxin Gao, D. F. Wong
   A graph based algorithm for optimal buffer insertion under accurate delay models. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:535-539 [Conf]
   
5. Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
   Maze Routing with Buffer Insertion under Transition Time Constraints. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:702-707 [Conf]
   
6. Youxin Gao, D. F. Wong
   Optimal shape function for a bi-directional wire under Elmore delay model. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1997, pp:622-627 [Conf]
   
7. Youxin Gao, D. F. Wong
   Shaping a VLSI wire to minimize delay using transmission line model. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:611-616 [Conf]
   
8. Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao
   Shaping interconnect for uniform current density. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2002, pp:254-259 [Conf]
   
9. Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee
   Explicit gate delay model for timing evaluation. [Citation Graph (0, 0)][DBLP]
   ISPD, 2003, pp:32-38 [Conf]
   
10. Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong
    Current Calculation on VLSI Signal Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:580-585 [Conf]
    
11. Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong
    IR Drop and Ground Bounce Awareness Timing Model. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:226-231 [Conf]
    
12. Youxin Gao, D. F. Wong
    Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:2, pp:165-178 [Journal]
    
13. Youxin Gao, Martin D. F. Wong
    Optimal shape function for a bidirectional wire under Elmore delay model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:994-999 [Journal]
    
14. Youxin Gao, Martin D. F. Wong
    Wire-sizing optimization with inductance consideration using transmission-line model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1759-1767 [Journal]
    
15. Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao
    Maze routing with buffer insertion under transition time constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:91-95 [Journal]