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Author:
D. F. Wong: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Youxin Gao, D. F. Wong
    A fast and accurate delay estimation method for buffered interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:533-538 [Conf]
  2. Youxin Gao, D. F. Wong
    Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:217-220 [Conf]
  3. Minghorng Lai, D. F. Wong
    Memory-efficient interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:198-202 [Conf]
  4. I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
    Integrated power supply planning and floorplanning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:589-594 [Conf]
  5. Xiaoping Tang, D. F. Wong
    FAST-SP: a fast algorithm for block placement based on sequence pair. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:521-526 [Conf]
  6. Fung Yu Young, D. F. Wong
    Slicing Floorplans with Boundary Constraint. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:17-20 [Conf]
  7. Yang Cai, D. F. Wong
    A Channel/Switchbox Definition Algorithm for Building-Block Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:638-641 [Conf]
  8. Yang Cai, D. F. Wong
    On Minimizing the Number of L-Shaped Channels. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:328-334 [Conf]
  9. Chung-Ping Chen, Yao-Wen Chang, D. F. Wong
    Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:405-408 [Conf]
  10. Chung-Ping Chen, Yao-Ping Chen, D. F. Wong
    Optimal Wire-Sizing Formular Under the Elmore Delay Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:487-490 [Conf]
  11. Chung-Ping Chen, D. F. Wong
    Optimal Wire-Sizing Function with Fringing Capacitance Consideration. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:604-607 [Conf]
  12. Chung-Ping Chen, D. F. Wong
    Error Bounded Padé Approximation via Bilinear Conformal Transformation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:7-12 [Conf]
  13. Jingsheng Cong, D. F. Wong
    How to Obtain More Compactable Channel Routing Solutions. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:663-666 [Conf]
  14. John F. Croix, D. F. Wong
    Blade and razor: cell and interconnect delay analysis using current-based models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:386-389 [Conf]
  15. John F. Croix, D. F. Wong
    A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:337-340 [Conf]
  16. Mohankumar Guruswamy, D. F. Wong
    A General Multi-Layer Area Router. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:335-340 [Conf]
  17. Madhukar R. Korupolu, K. K. Lee, D. F. Wong
    Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:708-711 [Conf]
  18. Glenn G. Lai, Donald S. Fussell, D. F. Wong
    HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:43-47 [Conf]
  19. Minghorng Lai, D. F. Wong
    Maze routing with buffer insertion and wiresizing. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:374-378 [Conf]
  20. Wai-Kei Mak, D. F. Wong
    On Optimal Board-Level Routing for FPGA-Based Logic Emulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:552-556 [Conf]
  21. Rajmohan Rajaraman, D. F. Wong
    Optimal Clustering for Delay Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:309-314 [Conf]
  22. Xiaoping Tang, D. F. Wong
    Floorplanning with alignment and performance constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:848-853 [Conf]
  23. Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy
    Delay Minimal Decomposition of Multiplexers in Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:254-257 [Conf]
  24. Khe-Sing The, D. F. Wong, Jason Cong
    VIA Minimization by Layout Modification. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:799-802 [Conf]
  25. Ruiqi Tian, D. F. Wong, Robert Boone
    Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:667-670 [Conf]
  26. Ting-Chi Wang, D. F. Wong
    An Optimal Algorithm for Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:180-186 [Conf]
  27. Ting-Chi Wang, D. F. Wong
    A Graph Theoretic Technique to Speed up Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:62-68 [Conf]
  28. D. F. Wong, C. L. Liu
    A new algorithm for floorplan design. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:101-107 [Conf]
  29. D. F. Wong, C. L. Liu
    Array Optimization for VLSI Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:537-543 [Conf]
  30. D. F. Wong, P. S. Sakhamuri
    Efficient Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:586-589 [Conf]
  31. Hua Xiang, D. F. Wong, Xiaoping Tang
    An algorithm for integrated pin assignment and buffer planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:584-589 [Conf]
  32. Hai Zhou, D. F. Wong
    Optimal low power X OR gate decomposition. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:104-107 [Conf]
  33. Hai Zhou, D. F. Wong
    Global Routing with Crosstalk Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:374-377 [Conf]
  34. Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
    Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:96-99 [Conf]
  35. Kai Zhu, D. F. Wong
    Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:165-170 [Conf]
  36. Kai Zhu, D. F. Wong
    Clock Skew Minimization During FPGA Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:232-237 [Conf]
  37. Chris C. N. Chu, D. F. Wong
    A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:479-0 [Conf]
  38. Youxin Gao, D. F. Wong
    Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:512-0 [Conf]
  39. Youxin Gao, D. F. Wong
    A graph based algorithm for optimal buffer insertion under accurate delay models. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:535-539 [Conf]
  40. Li-Da Huang, Hung-Ming Chen, D. F. Wong
    Global Wire Bus Configuration with Minimum Delay Uncertainty. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10050-10055 [Conf]
  41. Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
    Maze Routing with Buffer Insertion under Transition Time Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:702-707 [Conf]
  42. Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
    A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:470-477 [Conf]
  43. Minghorng Lai, D. F. Wong
    Slicing tree is a complete floorplan representation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:228-232 [Conf]
  44. I-Min Liu, Adnan Aziz, D. F. Wong
    Meeting Delay Constraints in DSM by Minimal Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:436-440 [Conf]
  45. Xiaoping Tang, D. F. Wong, Ruiqi Tian
    Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:106-111 [Conf]
  46. Yao-Wen Chang, D. F. Wong, C. K. Wong
    Universal Switch-Module Design for Symmetric-Array-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:80-86 [Conf]
  47. K. K. Lee, D. F. Wong
    LRoute: a delay minimal router for hierarchical CPLDs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:12-20 [Conf]
  48. K. K. Lee, D. F. Wong
    Incremental reconfiguration of multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:206-213 [Conf]
  49. Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
    Wire type assignment for FPGA routing. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:61-67 [Conf]
  50. Huiqun Liu, D. F. Wong
    Circuit Partitioning for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:187-194 [Conf]
  51. Huiqun Liu, Kai Zhu, D. F. Wong
    Circuit Partitioning with Complex Resource Constraints in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:77-84 [Conf]
  52. Wai-Kei Mak, D. F. Wong
    Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:260- [Conf]
  53. Shashidhar Thakur, D. F. Wong
    On Designing ULM-based FPGA Logic Modules. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:3-9 [Conf]
  54. Shashidhar Thakur, D. F. Wong
    Universal Logic Modules for Series-Parallel Functions. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:31-37 [Conf]
  55. Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
    Faster and more accurate wiring evaluation in interconnect-centric floorplanning. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:62-67 [Conf]
  56. Yang Cai, D. F. Wong
    An Optimal Channel Pin Assignment Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:10-13 [Conf]
  57. Yang Cai, D. F. Wong
    Minimizing Channel Density by Shifting Blocks and Terminals. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:524-527 [Conf]
  58. Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
    Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:617-624 [Conf]
  59. Yao-Wen Chang, Jai-Ming Lin, D. F. Wong
    Graph matching-based algorithms for FPGA segmentation design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:34-39 [Conf]
  60. Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
    A new global routing algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:356-361 [Conf]
  61. Kai-Yuan Chao, D. F. Wong
    Layer assignment for high-performance multi-chip modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:680-685 [Conf]
  62. Kai-Yuan Chao, D. F. Wong
    Signal integrity optimization on the pad assignment for high-speed VLSI design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:720-725 [Conf]
  63. Chung-Ping Chen, Hai Zhou, D. F. Wong
    Optimal non-uniform wire-sizing under the Elmore delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:38-43 [Conf]
  64. Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
    Integrated floorplanning and interconnect planning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:354-357 [Conf]
  65. Chris C. N. Chu, D. F. Wong
    A new approach to simultaneous buffer insertion and wire sizing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:614-621 [Conf]
  66. Yung-Ming Fang, D. F. Wong
    Simultaneous functional-unit binding and floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:317-321 [Conf]
  67. Youxin Gao, D. F. Wong
    Optimal shape function for a bi-directional wire under Elmore delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:622-627 [Conf]
  68. Youxin Gao, D. F. Wong
    Shaping a VLSI wire to minimize delay using transmission line model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:611-616 [Conf]
  69. Shinichiro Haruyama, D. F. Wong, Donald S. Fussell
    Topological Routing Using Geometric Information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:6-9 [Conf]
  70. T. W. Her, D. F. Wong
    Optimal Module Implementation and Its Application to Transistor Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:98-101 [Conf]
  71. T. W. Her, D. F. Wong, T. H. Freeman
    Optimal Orientations of Transistor Chains. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:524-527 [Conf]
  72. Huiqun Liu, D. F. Wong
    Network flow based circuit partitioning for time-multiplexed FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:497-504 [Conf]
  73. Huiqun Liu, D. F. Wong
    A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:400-405 [Conf]
  74. Wai-Kei Mak, D. F. Wong
    Board-level multi-terminal net routing for FPGA-based logic emulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:339-344 [Conf]
  75. Wai-Kei Mak, D. F. Wong
    Minimum replication min-cut partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:205-210 [Conf]
  76. Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao
    Shaping interconnect for uniform current density. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:254-259 [Conf]
  77. Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong
    A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:49-56 [Conf]
  78. Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong
    On mask layout partitioning for electron projection lithography. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:514-518 [Conf]
  79. Honghua Yang, D. F. Wong
    Efficient network flow based min-cut balanced partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:50-55 [Conf]
  80. Hannah Honghua Yang, D. F. Wong
    Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:150-155 [Conf]
  81. Hannah Honghua Yang, D. F. Wong
    New algorithms for min-cut replication in partitioned circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:216-222 [Conf]
  82. Fung Yu Young, D. F. Wong
    Slicing floorplans with pre-placed modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:252-258 [Conf]
  83. Jacob White, Jacob Avidan, Abe Elfadel, D. F. Wong
    Advances in transistor timing, simulation, and optimization (tutorial abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:611- [Conf]
  84. Hua Xiang, Kai-Yuan Chao, D. F. Wong
    ECO algorithms for removing overlaps between power rails and signal wires. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:67-74 [Conf]
  85. Hua Xiang, Xiaoping Tang, D. F. Wong
    An Algorithm for Simultaneous Pin Assignment and Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:232-0 [Conf]
  86. Hai Zhou, D. F. Wong
    An optimal algorithm for river routing with crosstalk constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:310-315 [Conf]
  87. Hai Zhou, D. F. Wong
    An exact gate decomposition algorithm for low-power technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:575-580 [Conf]
  88. Kai Zhu, D. F. Wong
    On channel segmentation design for row-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:26-29 [Conf]
  89. Kai Zhu, D. F. Wong, Yao-Wen Chang
    Switch module design with application to two-dimensional segmentation design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:480-485 [Conf]
  90. Yang Cai, D. F. Wong
    Channel Density Minimization by Pin Permutation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:378-382 [Conf]
  91. John C. Chan, Baxter F. Womack, D. F. Wong
    On the Manisfestation of Faults to Errors in Signature Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:360-363 [Conf]
  92. Yao-Wen Chang, D. F. Wong, C. K. Wong
    FPGA global routing based on a new congestion metric. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:372-0 [Conf]
  93. Yao-Wen Chang, D. F. Wong, C. K. Wong
    Design and analysis of FPGA/FPIC switch modules. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:394-401 [Conf]
  94. Kai-Yuan Chao, D. F. Wong
    Thermal placement for high-performance multichip modules. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:218-223 [Conf]
  95. Yao-Ping Chen, D. F. Wong
    On Retiming for FPGA Logic Module Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:394-397 [Conf]
  96. Yung-Ming Fang, D. F. Wong
    Multiplexor Network Generation in High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:78-0 [Conf]
  97. K. K. Lee, D. F. Wong
    An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:216-221 [Conf]
  98. I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
    An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:210-215 [Conf]
  99. Wai-Kei Mak, D. F. Wong
    Channel Segmentation Design for Symmentrical FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:496-501 [Conf]
  100. Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi
    Clustering and Load Balancing for Buffered Clock Tree Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:217-223 [Conf]
  101. Shashidhar Thakur, D. F. Wong
    Simultaneous area and delay minimum K-LUT mapping for K-exact networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:402-408 [Conf]
  102. Khe-Sing The, D. F. Wong
    Area Optimization for Higher Order Hierarchical Floorplans. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:520-523 [Conf]
  103. Fung Yu Young, D. F. Wong
    On the Construction of Universal Series-Parallel Functions for Logic Module Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:482-488 [Conf]
  104. Hai Zhou, D. F. Wong
    Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:628-633 [Conf]
  105. Kai-Yuan Chao, D. F. Wong
    Floorplanning for Low Power Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:45-48 [Conf]
  106. Yao-Ping Chen, D. F. Wong
    On optimal approximation of orthogonal polygons. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2533-2536 [Conf]
  107. Yao-Ping Chen, D. F. Wong
    A Graph Theoretic Approach to Feed-Through Pin Assignment. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1687-1690 [Conf]
  108. Yao-Ping Chen, Ting-Chi Wang, D. F. Wong
    A Graph Partitioning Problem for Multiple-chip Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1778-1781 [Conf]
  109. T. W. Her, D. F. Wong
    Over-the-Cell Routing with Cell Orientations Consideration. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:471-474 [Conf]
  110. Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
    An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:207-210 [Conf]
  111. Wai-Kei Mak, D. F. Wong
    A fast hypergraph minimum cut algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:170-173 [Conf]
  112. Yongseok Cheon, D. F. Wong
    Design hierarchy guided multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:30-35 [Conf]
  113. Chris C. N. Chu, D. F. Wong
    A matrix synthesis approach to thermal placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:163-168 [Conf]
  114. Chris C. N. Chu, D. F. Wong
    Closed form solution to simultaneous buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:192-197 [Conf]
  115. Chris C. N. Chu, D. F. Wong
    Greedy wire-sizing is linear time. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:39-44 [Conf]
  116. Seokjin Lee, D. F. Wong
    Timing-driven routing for FPGAs based on Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:176-181 [Conf]
  117. I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong
    Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:33-38 [Conf]
  118. Huiqun Liu, D. F. Wong
    Network flow based multi-way partitioning with area and pin constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:12-17 [Conf]
  119. Xiaoping Tang, D. F. Wong
    Planning buffer locations by network flows. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:180-185 [Conf]
  120. Ruiqi Tian, Xiaoping Tang, D. F. Wong
    Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:118-123 [Conf]
  121. Hua Xiang, Kai-Yuan Chao, D. F. Wong
    An ECO algorithm for eliminating crosstalk violations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:41-46 [Conf]
  122. Fung Yu Young, D. F. Wong
    How good are slicing floorplans?. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:144-149 [Conf]
  123. Fung Yu Young, D. F. Wong
    Slicing floorplans with range constraint. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:97-102 [Conf]
  124. D. F. Wong, C. L. Liu
    Floorplan Design of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1989, v:4, n:2, pp:263-291 [Journal]
  125. D. F. Wong, Edward M. Reingold
    Probabilistic Analysis of a Grouping Algorithm. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1991, v:6, n:2, pp:192-206 [Journal]
  126. Youxin Gao, D. F. Wong
    Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:2, pp:165-178 [Journal]
  127. Y. P. Chen, D. F. Wong
    On retiming for FPGA logic module minimization. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:24, n:2, pp:135-145 [Journal]
  128. Y. P. Chen, D. F. Wong
    A graph theoretic approach to feed-through pin assignment. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:24, n:2, pp:147-158 [Journal]
  129. Wai-Kei Mak, D. F. Wong
    A fast hypergraph min-cut algorithm for circuit partitioning. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:30, n:1, pp:1-11 [Journal]
  130. Xiaoping Tang, D. F. Wong
    Network flow based buffer planning. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:30, n:2, pp:143-155 [Journal]
  131. F. Y. Young, D. F. Wong
    How good are slicing floorplans? [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:23, n:1, pp:61-73 [Journal]
  132. Fung Yu Young, Chris C. N. Chu, D. F. Wong
    Generation of Universal Series-Parallel Boolean Functions. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1999, v:46, n:3, pp:416-435 [Journal]
  133. Yao-Wen Chang, D. F. Wong, C. K. Wong
    Universal switch modules for FPGA design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:1, pp:80-101 [Journal]
  134. Yao-Wen Chang, Kai Zhu, D. F. Wong
    Timing-driven routing for symmetrical array-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:433-450 [Journal]
  135. Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong
    Analysis of FPGA/FPIC switch modules. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:11-37 [Journal]
  136. Chris C. N. Chu, D. F. Wong
    Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:343-371 [Journal]
  137. Wai-Kei Mak, D. F. Wong
    Board-level multiterminal net routing for FPGA-based logic emulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:2, pp:151-167 [Journal]
  138. Shashidhar Thakur, D. F. Wong
    Series-parallel functions and FPGA logic module design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:1, pp:102-122 [Journal]
  139. Hai Zhou, D. F. Wong
    Optimal river routing with crosstalk constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:496-514 [Journal]

  140. Algorithms for a switch module routing problem. [Citation Graph (, )][DBLP]


  141. Optimal via-shifting in channel compaction. [Citation Graph (, )][DBLP]


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