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Milagros Sashikánth: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
    A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:791-794 [Conf]
  2. Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
    A function generator-based reconfigurable system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:905-909 [Conf]
  3. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1200-1203 [Conf]
  4. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:265- [Conf]
  5. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  6. Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
    An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:507-510 [Conf]
  7. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:736-741 [Conf]

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