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Daniel D. Gajski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski
    System-level communication modeling for network-on-chip synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:45-48 [Conf]
  2. Bita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski
    Designing a custom architecture for DCT using NISC technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:116-117 [Conf]
  3. Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski
    Automatic network generation for system-on-chip communication design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:255-260 [Conf]
  4. Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski
    Automatic generation of transaction level models for rapid design space exploration. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:64-69 [Conf]
  5. Daniel D. Gajski, Duncan H. Lawrie, David J. Kuck, Ahmed H. Sameh
    Cedar. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1984, pp:306-310 [Conf]
  6. Steven T. Healey, Daniel D. Gajski
    Decomposition of logic networks into silicon. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:162-168 [Conf]
  7. Samar Abdi, Daniel D. Gajski
    Functional Validation of System Level Static Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:542-547 [Conf]
  8. Shuqing Zhao, Daniel D. Gajski
    Defining an Enhanced RTL Semantics. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:548-553 [Conf]
  9. Daniel D. Gajski
    New Strategies for System-Level Design. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:15- [Conf]
  10. Bita Gorjiara, Daniel D. Gajski
    Custom Processor Design Using NISC: A Case-Study on DCT algorithm. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:55-60 [Conf]
  11. Smita Bakshi, Daniel D. Gajski
    Design exploration for high-performance pipelines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:312-316 [Conf]
  12. Hsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski
    Condition graphs for high-quality behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:170-174 [Conf]
  13. Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski
    Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:69-76 [Conf]
  14. Frank Vahid, Daniel D. Gajski
    Clustering for improved system-level functional partitioning. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:28-35 [Conf]
  15. Shuqing Zhao, Daniel D. Gajski
    Structural operational semantics for supporting multi-cycle operations in RTL HDLs. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:45-53 [Conf]
  16. Nikil D. Dutt, Daniel D. Gajski
    Design Synthesis and Silicon Compilation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:6, pp:8-23 [Journal]
  17. Daniel D. Gajski, Loganath Ramachandran
    Introduction to High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:44-54 [Journal]
  18. Daniel D. Gajski, Frank Vahid
    Specification and Design of Embedded Hardware-Software Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:1, pp:53-67 [Journal]
  19. Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
    System Specification with the SpecCharts Language. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:4, pp:6-13 [Journal]
  20. Forrest Brewer, Daniel D. Gajski
    Chippe: a system for constraint driven behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:681-695 [Journal]
  21. Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu
    Layout placement for sliced architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:102-114 [Journal]
  22. Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
    A transformation-based method for loop folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:439-450 [Journal]
  23. Youn-Long Lin, Daniel D. Gajski
    LES: a layout expert system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:868-876 [Journal]
  24. Chidchanok Lursinsap, Daniel D. Gajski
    A technique for pull-up transistor folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:887-896 [Journal]
  25. Allen C.-H. Wu, Daniel D. Gajski
    Partitioning algorithms for layout synthesis from register-transfer netlists. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:453-463 [Journal]
  26. Barry M. Pangrle, Daniel D. Gajski
    Design Tools for Intelligent Silicon Compilation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1098-1112 [Journal]
  27. Elke A. Rundensteiner, Daniel D. Gajski, Lubomir Bic
    Component synthesis from functional descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1287-1299 [Journal]
  28. Frank Vahid, Sanjiv Narayan, Daniel D. Gajski
    SpecCharts: a VHDL front-end for embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:694-706 [Journal]
  29. Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil
    TLM: Crossing Over From Buzz To Adoption. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:444-445 [Conf]
  30. Ines Viskic, Samar Abdi, Daniel D. Gajski
    Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:143-145 [Conf]
  31. Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski
    An Interactive Design Environment for C-based High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:135-144 [Conf]
  32. Frank Vahid, Daniel D. Gajski
    Incremental hardware estimation during hardware/software functional partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:459-464 [Journal]
  33. Jie Gong, Daniel D. Gajski, Alexandru Nicolau
    Performance evaluation for application-specific architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:4, pp:483-490 [Journal]
  34. Smita Bakshi, Daniel D. Gajski
    Component selection for high-performance pipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:181-194 [Journal]
  35. Daniel D. Gajski, Sanjiv Narayan, L. Ramachandran, Frank Vahid, P. Fung
    System design methodologies: aiming at the 100 h design cycle. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:70-82 [Journal]
  36. Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
    SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:84-100 [Journal]
  37. Smita Bakshi, Daniel D. Gajski
    Partitioning and pipelining for performance-constrained hardware/software systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:419-432 [Journal]
  38. Jianwen Zhu, Daniel D. Gajski
    An ultra-fast instruction set simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:363-373 [Journal]

  39. Accurate timed RTOS model for transaction level modeling. [Citation Graph (, )][DBLP]


  40. Closeness metrics for system-level functional partitioning. [Citation Graph (, )][DBLP]


  41. A memory selection algorithm for high-performance pipelines. [Citation Graph (, )][DBLP]


  42. A transformation for integrating VHDL behavioral specification with synthesis and software generation. [Citation Graph (, )][DBLP]


  43. A component selection algorithm for high-performance pipelines. [Citation Graph (, )][DBLP]


  44. 100-hour design cycle: a test case. [Citation Graph (, )][DBLP]


  45. A performance evaluator for parameterized ASIC architectures. [Citation Graph (, )][DBLP]


  46. A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. [Citation Graph (, )][DBLP]


  47. Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor. [Citation Graph (, )][DBLP]


  48. Model Based Synthesis of Embedded Software. [Citation Graph (, )][DBLP]


  49. Custom Processor Core Construction from C Code. [Citation Graph (, )][DBLP]


  50. An Introduction to High-Level Synthesis. [Citation Graph (, )][DBLP]


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