The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Indradeep Ghosh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Indradeep Ghosh, Krishna Sekar, Vamsi Boppana
    Design for Verification at the Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:420-425 [Conf]
  2. Indradeep Ghosh
    High Level Test Generation for Custom Hardware: An Industrial Perspective. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:458- [Conf]
  3. Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
    Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:148-153 [Conf]
  4. Indradeep Ghosh, Sujit Dey, Niraj K. Jha
    A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:542-547 [Conf]
  5. Indradeep Ghosh, Masahiro Fujita
    Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:43-48 [Conf]
  6. Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
    A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:554-559 [Conf]
  7. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:534-539 [Conf]
  8. Indradeep Ghosh, Srivaths Ravi
    On automatic generation of RTL validation test benches using circuit testing techniques. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:289-294 [Conf]
  9. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    A design for testability technique for RTL circuits using control/data flow extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:329-336 [Conf]
  10. Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh
    Precomputation-based Guarding for Dynamic and Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:90-97 [Conf]
  11. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:173-179 [Conf]
  12. Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
    A Technique for Identifying RTL and Gate-Level Correspondences. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:591-0 [Conf]
  13. Indradeep Ghosh, Mukul R. Prasad
    A Technique for Estimating the Difficulty of a Formal Verification Problem. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:63-70 [Conf]
  14. Indradeep Ghosh, Niraj K. Jha, Sujit Dey
    A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:50-59 [Conf]
  15. Liang Zhang, Indradeep Ghosh, Michael S. Hsiao
    Efficient Sequential ATPG for Functional RTL Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:290-298 [Conf]
  16. Sudipta Bhawmik, Indradeep Ghosh
    A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:284-288 [Conf]
  17. Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
    Hierarchical Error Diagnosis Targeting RTL Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:436-441 [Conf]
  18. Indradeep Ghosh, Bandana Majumdar
    Design of an Application Specific VLSI Chip for Image Rotation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:275-278 [Conf]
  19. Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita
    High Level Design Validation: Current Practices and Future Directions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:9-11 [Conf]
  20. Indradeep Ghosh, Krishna Sekar, Vamsi Boppana
    Design for Verification at the Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:420-425 [Conf]
  21. Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
    Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:193-198 [Conf]
  22. Indradeep Ghosh, Bandana Majumdar
    VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:449-462 [Journal]
  23. Indradeep Ghosh, Niraj K. Jha
    High-level test synthesis: a survey. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:79-99 [Journal]
  24. Indradeep Ghosh, Sujit Dey, Niraj K. Jha
    A fast and low-cost testing technique for core-based system-chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:863-877 [Journal]
  25. Indradeep Ghosh, Masahiro Fujita
    Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:402-415 [Journal]
  26. Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
    A BIST scheme for RTL circuits based on symbolic testabilityanalysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:111-128 [Journal]
  27. Indradeep Ghosh, Niraj K. Jha, Sujit Dey
    A low overhead design for testability and test generation technique for core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1661-1676 [Journal]
  28. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1001-1014 [Journal]
  29. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    A design-for-testability technique for register-transfer level circuits using control/data flow extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:706-723 [Journal]
  30. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Hierarchical test generation and design for testability methods for ASPPs and ASIPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:357-370 [Journal]
  31. Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
    Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1414-1425 [Journal]
  32. Liang Zhang, Indradeep Ghosh, Michael S. Hsiao
    A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2526-2538 [Journal]

  33. Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution. [Citation Graph (, )][DBLP]


  34. WEAVE: WEb Applications Validation Environment. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.305secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002