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Norbert Wehn: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Frank Gilbert, Alexander Worm, Norbert Wehn
    Low power implementation of a turbo-decoder on programmable architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:400-403 [Conf]
  2. Frank Kienle, Norbert Wehn
    Design methodology for IRA codes. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:459-462 [Conf]
  3. Johannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp
    The ALGIC Silicon Compiler System: Implementation, Design Experience and Results. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:370-375 [Conf]
  4. Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth
    A Defect-Tolerant and Fully Testable PLA. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:22-33 [Conf]
  5. Norbert Wehn
    Power Optimization in advanced Channel Coding. [Citation Graph (0, 0)][DBLP]
    Power-aware Computing Systems, 2005, pp:- [Conf]
  6. Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn
    Channel Decoder Architecture for 3G Mobile Wireless Terminals. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:192-197 [Conf]
  7. Torben Brack, Frank Kienle, Norbert Wehn
    Disclosing the LDPC code decoder design space. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:200-205 [Conf]
  8. Frank Gilbert, Michael J. Thul, Norbert Wehn
    Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10356-10363 [Conf]
  9. Frank Kienle, Torben Brack, Norbert Wehn
    A Synthesizable IP Core for DVB-S2 LDPC Code Decoding. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:100-105 [Conf]
  10. Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch
    Hardware/Software Trade-Offs for Advanced 3G Channel Coding. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:396-401 [Conf]
  11. Michael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch
    Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:624-0 [Conf]
  12. Norbert Wehn, Søren Hein
    Embedded DRAM Architectural Trade-Offs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:704-708 [Conf]
  13. Alexander Worm, Holger Lamm, Norbert Wehn
    Design of low-power high-speed maximum a priori decoder architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:258-267 [Conf]
  14. Christian Neeb, Norbert Wehn
    Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:665-672 [Conf]
  15. Bernd Wurth, Norbert Wehn
    Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:630-634 [Conf]
  16. U. Zahm, Thomas Hollstein, Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner
    Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:241-250 [Conf]
  17. Christian Neeb, Norbert Wehn
    Energieminimierung von Basisbandsignalverarbeitungsalgorithmen auf programmierbaren Plattformen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:442- [Conf]
  18. J. Biesenack, Norbert Wehn, A. Stoll, Michael Payer
    Data Part Optimizations in the CALLAS Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:263-274 [Conf]
  19. Christian Neeb, Michael J. Thul, Norbert Wehn
    Network-on-chip-centric approach to interleaving in high throughput channel decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1766-1769 [Conf]
  20. Michael J. Thul, Norbert Wehn, L. P. Rao
    Enabling high-speed turbo-decoding through concurrent interleaving. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:897-900 [Conf]
  21. Doris Keitel-Schulz, Norbert Wehn
    Issues in Embedded DRAM Development and Applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:23-30 [Conf]
  22. Michael Münch, Manfred Glesner, Norbert Wehn
    An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:45-50 [Conf]
  23. Norbert Wehn
    Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:3- [Conf]
  24. Norbert Wehn, Manfred Glesner, A. Kister, S. Kastner
    Timing Driven Partitioning of Combinational Logic. [Citation Graph (0, 0)][DBLP]
    Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1990, pp:42-51 [Conf]
  25. Frank Gilbert, Norbert Wehn
    Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:379-388 [Conf]
  26. Armin Wellig, Julien Zory, Norbert Wehn
    Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:218-227 [Conf]
  27. Timo Vogt, Christian Neeb, Norbert Wehn
    A Reconfigurable Multi-Processor Platform for Convolutional and Turbo Decoding. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:16-23 [Conf]
  28. Michael J. Thul, Norbert Wehn
    FPGA implementation of parallel turbo-decoders. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:198-203 [Conf]
  29. Timo Vogt, Norbert Wehn, Philippe Alves
    A multi-standard channel-decoder for base-station applications. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:192-197 [Conf]
  30. A. Laudenbach, Manfred Glesner, Norbert Wehn
    A VLSI System Design for the Control of High Performance Combustion Engines. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:247-256 [Conf]
  31. Norbert Wehn, Manfred Glesner, C. Vielhauer
    Estimating lower hardware bounds in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:261-270 [Conf]
  32. Norbert Wehn, J. Biesenack, Michael Pilsl
    A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:203-213 [Conf]
  33. Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda
    Embedded Memories in System Design: Technology, Application, Design and Tools. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:5-6 [Conf]
  34. Alexander Worm, Holger Lamm, Norbert Wehn
    Vlsi Architectures For High-Speed Map Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:446-453 [Conf]
  35. Doris Keitel-Schulz, Norbert Wehn
    Embedded DRAM Development: Technology, Physical Design, and Application Issues. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:3, pp:7-15 [Journal]
  36. Norbert Wehn
    System-on-Chip - Ein Sonderheft anlässlich des 60. Geburtstages von Prof. Dr. Dr. h.c. mult. Manfred Glesner. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2003, v:45, n:6, pp:- [Journal]
  37. Norbert Wehn
    Vergleich von Hardware- und Software-Implementierungen in der digitalen Kommunikation am Beispiel der Kanalcodierung. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2003, v:45, n:6, pp:- [Journal]
  38. Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn
    The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:12, pp:1398-1406 [Journal]
  39. Michael Münch, Norbert Wehn, Manfred Glesner
    An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:4, pp:344-364 [Journal]
  40. Torben Brack, M. Alles, T. Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci
    Low complexity LDPC code decoders for next generation standards. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:331-336 [Conf]
  41. Matthias May, Christian Neeb, Norbert Wehn
    Evaluation of High Throughput Turbo-Decoder Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2770-2773 [Conf]
  42. Zoltán Herczeg, Ákos Kiss, Daniel Schmidt, Norbert Wehn, Tibor Gyimóthy
    XEEMU: An Improved XScale Power Simulator. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:300-309 [Conf]
  43. J. Biesenack, M. Koster, A. Langmaier, S. Ledeux, S. Marz, Michael Payer, Michael Pilsl, S. Rumler, H. Soukup, Norbert Wehn, P. Duzy
    The Siemens high-level synthesis system CALLAS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:244-253 [Journal]

  44. A Reconfigurable Outer Modem Platform for Future Communications Systems. [Citation Graph (, )][DBLP]

  45. A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder. [Citation Graph (, )][DBLP]

  46. A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment. [Citation Graph (, )][DBLP]

  47. A novel LDPC decoder for DVB-S2 IP. [Citation Graph (, )][DBLP]

  48. Error correction in single-hop wireless sensor networks - A case study. [Citation Graph (, )][DBLP]

  49. A 150Mbit/s 3GPP LTE Turbo code decoder. [Citation Graph (, )][DBLP]

  50. A rapid prototyping system for error-resilient multi-processor systems-on-chip. [Citation Graph (, )][DBLP]

  51. Scheduling of behavioral VHDL by retiming techniques. [Citation Graph (, )][DBLP]

  52. Application-specific reconfigurable processors. [Citation Graph (, )][DBLP]

  53. 3.1-to-7GHz UWB impulse radio transceiver front-end based on statistical correlation technique. [Citation Graph (, )][DBLP]

  54. DRAM power management and energy consumption: a critical assessment. [Citation Graph (, )][DBLP]

  55. A Survey on LDPC Codes and Decoders for OFDM-based UWB Systems. [Citation Graph (, )][DBLP]

  56. A Reliability-Aware LDPC Code Decoding Algorithm. [Citation Graph (, )][DBLP]

  57. Fast convergence algorithm for LDPC Codes. [Citation Graph (, )][DBLP]

  58. Macro Interleaver Design for Bit Interleaved Coded Modulation with Low-Density Parity-Check Codes. [Citation Graph (, )][DBLP]

  59. Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking. [Citation Graph (, )][DBLP]

  60. A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding. [Citation Graph (, )][DBLP]

  61. A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding. [Citation Graph (, )][DBLP]

  62. A Separation Algorithm for Improved LP-Decoding of Linear Block Codes [Citation Graph (, )][DBLP]

  63. On Complexity, Energy- and Implementation-Efficiency of Channel Decoders [Citation Graph (, )][DBLP]

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