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Title:
Author:
Frank Vahid: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tony Givargis, Frank Vahid, Jörg Henkel
    A hybrid approach for core-based system-level power modeling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:141-146 [Conf]
  2. Tony Givargis, Frank Vahid, Jörg Henkel
    Trace-driven system-level power evaluation of system-on-a-chip peripheral cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:306-312 [Conf]
  3. Ann Gordon-Ross, Frank Vahid
    Frequent loop detection using efficient non-intrusive on-chip hardware. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:117-124 [Conf]
  4. Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky
    A first-step towards an architecture tuning methodology for low power. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:187-192 [Conf]
  5. Susan Cotterell, Frank Vahid
    A logic block enabling logic configuration by non-experts in sensor networks. [Citation Graph (0, 0)][DBLP]
    CHI Extended Abstracts, 2005, pp:1925-1928 [Conf]
  6. Brian Grattan, Greg Stitt, Frank Vahid
    Codesign-extended applications. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:1-6 [Conf]
  7. Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh
    First results with eBlocks: embedded systems building blocks. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:168-175 [Conf]
  8. Tony Givargis, Frank Vahid
    Parameterized system design. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:98-102 [Conf]
  9. Roman L. Lysecky, Frank Vahid
    A codesigned on-chip logic minimizer. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:109-113 [Conf]
  10. Greg Stitt, Frank Vahid, Gordon McGregor, Brian Einloth
    Hardware/software partitioning of software binaries: a case study of H.264 decode. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:285-290 [Conf]
  11. Frank Vahid
    Modifying Min-Cut for Hardware and Software Functional Partitioning. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:43-48 [Conf]
  12. Frank Vahid, Tony Givargis
    The case for a configure-and-execute paradigm. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:59-63 [Conf]
  13. Frank Vahid, Thuy Dm Le
    Towards a Model for Hardware and Software Functional Partitioning. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:116-123 [Conf]
  14. Frank Vahid, Linus Tauro
    An Object-Oriented Communication Library for Hardware-Software CoDesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:81-86 [Conf]
  15. Daniel Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
    System-level exploration with SpecSyn. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:812-817 [Conf]
  16. Roman L. Lysecky, Susan Cotterell, Frank Vahid
    A fast on-chip profiler memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:28-33 [Conf]
  17. Roman L. Lysecky, Frank Vahid
    On-chip logic minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:334-337 [Conf]
  18. Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
    Dynamic FPGA routing for just-in-time FPGA compilation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:954-959 [Conf]
  19. Greg Stitt, Roman L. Lysecky, Frank Vahid
    Dynamic hardware/software partitioning: a first approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:250-255 [Conf]
  20. Frank Vahid, Daniel Gajski
    Specification Partitioning for System Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:219-224 [Conf]
  21. Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid
    Configurable cache subsetting for fast cache tuning. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:695-700 [Conf]
  22. Ann Gordon-Ross, Frank Vahid, Nikil Dutt
    Automatic Tuning of Two-Level Caches to Embedded Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:208-213 [Conf]
  23. Jörg Henkel, Tony Givargis, Frank Vahid
    Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:333-0 [Conf]
  24. Enoch Hwang, Frank Vahid, Yu-Chin Hsu
    FSMD Functional Partitioning for Low Power. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:22-27 [Conf]
  25. Roman L. Lysecky, Frank Vahid
    A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:480-485 [Conf]
  26. Roman L. Lysecky, Frank Vahid
    A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:18-23 [Conf]
  27. Roman L. Lysecky, Frank Vahid, Tony Givargis
    Techniques for Reducing Read Latency of Core Bus Wrappers. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:84-91 [Conf]
  28. Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid
    System Synthesis for Networks of Programmable Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:888-893 [Conf]
  29. Greg Stitt, Frank Vahid
    A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:396-397 [Conf]
  30. Chuanjun Zhang, Frank Vahid
    Using a Victim Buffer in an Application-Specific Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:220-227 [Conf]
  31. Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
    A Self-Tuning Cache Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:142-147 [Conf]
  32. Chuanjun Zhang, Jun Yang, Frank Vahid
    Low Static-Power Frequent-Value Data Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:214-219 [Conf]
  33. Daniel Gajski, Frank Vahid, Sanjiv Narayan
    A System-Design Methodology: Executable-Specification Refinement. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:458-463 [Conf]
  34. Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
    A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:57-62 [Conf]
  35. Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid
    Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:143-151 [Conf]
  36. Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers
    A quantitative analysis of the speedup factors of FPGAs over processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:162-170 [Conf]
  37. Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers
    Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:271- [Conf]
  38. Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
    Techniques for synthesizing binaries to an advanced register/memory structure. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:118-124 [Conf]
  39. Frank Vahid
    I/O and Performance Tradeoffs with the FunctionBus During Multi-FPGA Partitioning. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:27-34 [Conf]
  40. Ann Gordon-Ross, Frank Vahid, Nikil Dutt
    A first look at the interplay of code reordering and configurable caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:416-421 [Conf]
  41. Susan Lysecky, Frank Vahid
    Automated Generation of Basic Custom Sensor-Based Embedded Computing Systems Guided by End-User Optimization Criteria. [Citation Graph (0, 0)][DBLP]
    Ubicomp, 2006, pp:69-86 [Conf]
  42. Susan Lysecky, Frank Vahid
    Automated Application-Specific Tuning of Parameterized Sensor-Based Embedded System Building Blocks. [Citation Graph (0, 0)][DBLP]
    Ubicomp, 2006, pp:507-524 [Conf]
  43. Susan Cotterell, Frank Vahid
    Synthesis of customized loop caches for core-based embedded systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:655-662 [Conf]
  44. Tony Givargis, Jörg Henkel, Frank Vahid
    Interface and cache power exploration for core-based embedded system design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:270-273 [Conf]
  45. Tony Givargis, Frank Vahid, Jörg Henkel
    System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:25-30 [Conf]
  46. Sanjiv Narayan, Frank Vahid, Daniel Gajski
    System Specification and Synthesis with the SpecCharts Language. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:266-269 [Conf]
  47. Greg Stiff, Frank Vahid
    New decompilation techniques for binary-level co-processor generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:547-554 [Conf]
  48. Greg Stitt, Frank Vahid
    Hardware/software partitioning of software binaries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:164-170 [Conf]
  49. Frank Vahid, Daniel Gajski
    Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:362-365 [Conf]
  50. David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen
    Application-specific customization of parameterized FPGA soft-core processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:261-268 [Conf]
  51. David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky
    Conjoining soft-core FPGA processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:694-701 [Conf]
  52. Greg Stitt, Frank Vahid, Walid A. Najjar
    A code refinement methodology for performance-improved synthesis from C. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:716-723 [Conf]
  53. Ann Gordon-Ross, Frank Vahid
    Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:446-449 [Conf]
  54. Susan Cotterell, Ryan Mannion, Frank Vahid, Harry Hsieh
    eBlocks - an enabling technology for basic sensor based systems. [Citation Graph (0, 0)][DBLP]
    IPSN, 2005, pp:422-427 [Conf]
  55. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    A Highly-Configurable Cache Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:136-146 [Conf]
  56. Chuanjun Zhang, Frank Vahid
    A power-configurable bus for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:809-812 [Conf]
  57. Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
    Fast configurable-cache tuning with a unified second-level cache. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:323-326 [Conf]
  58. Frank Vahid, Ann Gordon-Ross
    A self-optimizing embedded microprocessor using a loop table for low power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:219-224 [Conf]
  59. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A way-halting cache for low-energy high-performance systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:126-131 [Conf]
  60. Tony Givargis, Frank Vahid
    Interface Exploration for Reduced Power in Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:117-124 [Conf]
  61. Roman L. Lysecky, Frank Vahid, Tony Givargis
    Experiments with the Peripheral Virtual Component Interface. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:221-224 [Conf]
  62. Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis
    Pre-Fetching for Improved Core Interfacing. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:51-55 [Conf]
  63. Tony Givargis, Frank Vahid, Jörg Henkel
    Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:163-171 [Conf]
  64. Frank Vahid
    Procedure exlining: a transformation for improved system and behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:84-89 [Conf]
  65. Frank Vahid, Daniel D. Gajski
    Clustering for improved system-level functional partitioning. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:28-35 [Conf]
  66. Frank Vahid
    Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:107-112 [Conf]
  67. Frank Vahid
    A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:152-157 [Conf]
  68. Frank Vahid, Susan Cotterell
    Tuning of Loop Cache Architectures to Programs in Embedded System Design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:8-13 [Conf]
  69. Frank Vahid, Tony Givargis
    Incorporating Cores into System-Level Specification. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:43-50 [Conf]
  70. Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
    A Comparison of Functional and Structural Partitioning. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:121-126 [Conf]
  71. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    Energy Benefits of a Configurable Line Size Cache for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:87-91 [Conf]
  72. Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt
    Profiling tools for hardware/software partitioning of embedded applications. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:189-198 [Conf]
  73. Frank Vahid
    Embedded System Design: UCR's Undergraduate Three-Course Sequence. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:72-73 [Conf]
  74. Chuanjun Zhang, Frank Vahid
    Cache Configuration Exploration on Prototyping Platforms. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:164-0 [Conf]
  75. Ann Gordon-Ross, Susan Cotterell, Frank Vahid
    Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
  76. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A Way-Halting Cache for Low-Energy High-Performance Systems. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  77. Frank Vahid
    The Softening of Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:27-34 [Journal]
  78. Frank Vahid, Tony Givargis
    Platform Tuning for Embedded Systems Design. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:3, pp:112-114 [Journal]
  79. Daniel D. Gajski, Frank Vahid
    Specification and Design of Embedded Hardware-Software Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:1, pp:53-67 [Journal]
  80. Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
    System Specification with the SpecCharts Language. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:4, pp:6-13 [Journal]
  81. Greg Stitt, Frank Vahid
    Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:36-43 [Journal]
  82. Frank Vahid
    Making the Best of Those Extra Transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:96-0 [Journal]
  83. Frank Vahid, Tony Givargis, Susan Cotterell
    Power Estimator Development for Embedded System Memory Tuning. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:5, pp:459-476 [Journal]
  84. Frank Vahid, Rilesh Patel, Greg Stitt
    Propagating constants past software to hardware peripherals in fixed-application embedded systems. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:5, pp:25-30 [Journal]
  85. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A way-halting cache for low-energy high-performance systems. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:1, pp:34-54 [Journal]
  86. Ann Gordon-Ross, Frank Vahid
    Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:10, pp:1203-1215 [Journal]
  87. Tony Givargis, Frank Vahid
    Platune: a tuning framework for system-on-a-chip platforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1317-1327 [Journal]
  88. Frank Vahid
    Techniques for minimizing and balancing I/O during functional partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:69-75 [Journal]
  89. Frank Vahid, Sanjiv Narayan, Daniel D. Gajski
    SpecCharts: a VHDL front-end for embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:694-706 [Journal]
  90. Greg Stitt, Frank Vahid, Shawn Nematbakhsh
    Energy savings and speedups from partitioning critical software loops to hardware in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:218-232 [Journal]
  91. Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
    A self-tuning cache architecture for embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:407-425 [Journal]
  92. Ann Gordon-Ross, Susan Cotterell, Frank Vahid
    Tiny instruction caches for low power embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:4, pp:449-481 [Journal]
  93. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    A highly configurable cache for low energy embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:2, pp:363-387 [Journal]
  94. Roman L. Lysecky, Frank Vahid
    Prefetching for improved bus wrapper performance in cores. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:58-90 [Journal]
  95. Frank Vahid
    Partitioning sequential programs for CAD using a three-step approach. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:3, pp:413-429 [Journal]
  96. Frank Vahid
    Procedure cloning: a transformation for improved system-level functional partitioning. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:1, pp:70-96 [Journal]
  97. Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
    Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:181-208 [Journal]
  98. Roman L. Lysecky, Greg Stitt, Frank Vahid
    Warp Processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:659-681 [Journal]
  99. Roman L. Lysecky, Susan Cotterell, Frank Vahid
    A fast on-chip profiler memory using a pipelined binary tree. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:120-122 [Journal]
  100. Ann Gordon-Ross, Frank Vahid
    A Self-Tuning Configurable Cache. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:234-237 [Conf]
  101. David Sheldon, Frank Vahid, Stefano Lonardi
    Interactive presentation: Soft-core processor customization using the design of experiments paradigm. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:821-826 [Conf]
  102. Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid
    Clock-frequency assignment for multiple clock domain systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:397-402 [Conf]
  103. Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros
    A one-shot configurable-cache tuner for improved energy and performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:755-760 [Conf]
  104. Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid
    Two-level microprocessor-accelerator partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:313-318 [Conf]
  105. Scott Sirowy, Frank Vahid
    Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:145-154 [Conf]
  106. Greg Stitt, Frank Vahid
    A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  107. Roman L. Lysecky, Frank Vahid
    A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  108. Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid
    System Synthesis for Networks of Programmable Blocks [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  109. Greg Stitt, Frank Vahid
    Binary synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  110. Frank Vahid, Daniel D. Gajski
    Incremental hardware estimation during hardware/software functional partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:459-464 [Journal]
  111. Daniel D. Gajski, Sanjiv Narayan, L. Ramachandran, Frank Vahid, P. Fung
    System design methodologies: aiming at the 100 h design cycle. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:70-82 [Journal]
  112. Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
    SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:84-100 [Journal]
  113. T. D. Givargis, Frank Vahid, Jörg Henkel
    Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:500-508 [Journal]
  114. Tony Givargis, Frank Vahid, Jörg Henkel
    Instruction-based system-level power evaluation of system-on-a-chip peripheral cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:856-863 [Journal]
  115. Tony Givargis, Frank Vahid, Jörg Henkel
    System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:416-422 [Journal]
  116. Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt
    Highly configurable platforms for embedded computing systems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:11, pp:1025-1029 [Journal]

  117. Dynamic coprocessor management for FPGA-enhanced compute platforms. [Citation Graph (, )][DBLP]


  118. Thread warping: a framework for dynamic synthesis of thread accelerators. [Citation Graph (, )][DBLP]


  119. Dynamic tuning of configurable architectures: the AWW online algorithm. [Citation Graph (, )][DBLP]


  120. Highly-cited ideas in system codesign and synthesis. [Citation Graph (, )][DBLP]


  121. Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs. [Citation Graph (, )][DBLP]


  122. Portable SystemC-on-a-chip. [Citation Graph (, )][DBLP]


  123. Transmuting coprocessors: dynamic loading of FPGA coprocessors. [Citation Graph (, )][DBLP]


  124. Online SystemC emulation acceleration. [Citation Graph (, )][DBLP]


  125. Procedure cloning: a transformation for improved system-level functional partitioning. [Citation Graph (, )][DBLP]


  126. Closeness metrics for system-level functional partitioning. [Citation Graph (, )][DBLP]


  127. Procedure exlining: a new system-level specification transformation. [Citation Graph (, )][DBLP]


  128. A transformation for integrating VHDL behavioral specification with synthesis and software generation. [Citation Graph (, )][DBLP]


  129. 100-hour design cycle: a test case. [Citation Graph (, )][DBLP]


  130. A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. [Citation Graph (, )][DBLP]


  131. C is for circuits: capturing FPGA circuits as sequential code for portability. [Citation Graph (, )][DBLP]


  132. A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design. [Citation Graph (, )][DBLP]


  133. Making good points: application-specific pareto-point generation for design space exploration using statistical methods. [Citation Graph (, )][DBLP]


  134. Server-side coprocessor updating for mobile devices with FPGAs. [Citation Graph (, )][DBLP]


  135. Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. [Citation Graph (, )][DBLP]


  136. A table-based method for single-pass cache optimization. [Citation Graph (, )][DBLP]


  137. It's Time to Stop Calling Circuits "Hardware". [Citation Graph (, )][DBLP]


  138. Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. [Citation Graph (, )][DBLP]


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