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Hamid Mahmoodi-Meimand: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
    Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:665-670 [Conf]
  2. Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy
    Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:176-181 [Conf]
  3. Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy
    A novel synthesis approach for active leakage power reduction using dynamic supply gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:479-484 [Conf]
  4. Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia
    Low power synthesis of dynamic logic circuits using fine-grained clock gating. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:862-867 [Conf]
  5. Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
    A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1136-1141 [Conf]
  6. Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
    First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:314-315 [Conf]
  7. Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy
    Energy recovery clocked dynamic logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:468-471 [Conf]
  8. Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi
    A high speed and leakage-tolerant domino logic for high fan-in gates. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:478-481 [Conf]
  9. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    Statistical design and optimization of SRAM cell for yield enhancement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:10-13 [Conf]
  10. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-gate SOI devices for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:217-224 [Conf]
  11. Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
    Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:206-214 [Conf]
  12. Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
    A Novel Low-Power Scan Design Technique Using Supply Gating. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:60-65 [Conf]
  13. Aliakbar Ghadiri, Hamid Mahmoodi-Meimand
    Pre-capturing static pulsed flip-flops. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2421-2424 [Conf]
  14. Hamid Mahmoodi-Meimand, Ali Afzali-Kusha
    Efficient power clock generation for adiabatic logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:642-645 [Conf]
  15. Hamid Mahmoodi-Meimand, Kaushik Roy
    Data-retention flip-flops for power-down applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:677-680 [Conf]
  16. Hamid Mahmoodi-Meimand, Kaushik Roy
    Dual-edge triggered level converting flip-flops. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:661-664 [Conf]
  17. Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
    Energy recovery clocking scheme and flip-flops for ultra low-energy applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:54-59 [Conf]
  18. Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy
    High performance and low power FIR filter design based on sharing multiplication. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:295-300 [Conf]
  19. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy
    Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:453-458 [Conf]
  20. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:490-495 [Conf]
  21. Aliakbar Ghadiri, Hamid Mahmoodi-Meimand
    Dual-Edge Triggered Static Pulsed Flip-Flops. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:846-849 [Conf]
  22. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-Gate SOI Devices for Low-Power and High-Performance Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:445-452 [Conf]
  23. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
    Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:292-297 [Conf]
  24. Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
    Leakage Current in Deep-Submicron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:6, pp:575-600 [Journal]
  25. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1859-1880 [Journal]
  26. Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy
    A process-tolerant cache architecture for improved yield in nanoscale technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:27-38 [Journal]
  27. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy
    Low-power scan design using first-level supply gating. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:384-395 [Journal]
  28. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1286-1295 [Journal]
  29. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
    A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:183-192 [Journal]

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