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Huawei Li: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li
    Design of an efficient memory subsystem for network processor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:897-900 [Conf]
  2. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
    Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:53-58 [Conf]
  3. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Rapid and Energy-Efficient Testing for Embedded Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:8-13 [Conf]
  4. Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:440-445 [Conf]
  5. Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li
    Pair Balance-Based Test Scheduling for SOCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:236-241 [Conf]
  6. Huawei Li, Zhongcheng Li, Yinghua Min
    Delay Testing with Double Observations. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:96-0 [Conf]
  7. Huawei Li, Yinghua Min, Zhongcheng Li
    An RT-Level ATPG Based on Clustering of Circuit States. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:213-218 [Conf]
  8. Huawei Li, Yue Zhang, Xiaowei Li
    Delay Test Pattern Generation Considering Crosstalk-Induced Effects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:178-183 [Conf]
  9. Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min
    Test Power Optimization Techniques for CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:332-337 [Conf]
  10. Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li
    Non-robust Test Generation for Crosstalk-Induced Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:120-125 [Conf]
  11. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:298-305 [Conf]
  12. Xiaowei Li, Huawei Li, Yinghua Min
    Reducing Power Dissipation during At-Speed Test Application. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:116-0 [Conf]
  13. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
    Using MUXs Network to Hide Bunches of Scan Chains. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:238-243 [Conf]
  14. Yu Hu, Xiaowei Li, Huawei Li, Xiao-Qing Wen
    Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:175-182 [Conf]
  15. Huawei Li, Pei-Fu Shen, Xiaowei Li
    Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:300-305 [Conf]
  16. Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
    Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:201-209 [Journal]
  17. Zhigang Yin, Yinghua Min, Xiaowei Li, Huawei Li
    A Novel RT-Level Behavioral Description Based ATPG Method. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:3, pp:308-317 [Journal]
  18. Lei Zhang, Huawei Li, Xiaowei Li
    A Routing Algorithm for Random Error Tolerance in Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    HCI (4), 2007, pp:1210-1219 [Conf]
  19. Huawei Li, Yu Fan, Tao Wu
    Impact of Load Characteristics and Low-Voltage Load Shedding Schedule on Dynamic Voltage Stability. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:2249-2252 [Conf]
  20. Huawei Li, Yu Fan, Rong Shi
    Chaos and Ferroresonance. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:494-497 [Conf]
  21. Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han
    Fast Packet Classification using Group Bit Vector. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  22. Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra
    Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:531-540 [Journal]
  23. Huawei Li, Xiaowei Li
    Selection of Crosstalk-Induced Faults in Enhanced Delay Test. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:181-195 [Journal]

  24. A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. [Citation Graph (, )][DBLP]


  25. Robust test generation for power supply noise induced path delay faults. [Citation Graph (, )][DBLP]


  26. M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. [Citation Graph (, )][DBLP]


  27. A Low Overhead On-Chip Path Delay Measurement Circuit. [Citation Graph (, )][DBLP]


  28. A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. [Citation Graph (, )][DBLP]


  29. Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. [Citation Graph (, )][DBLP]


  30. An on-chip clock generation scheme for faster-than-at-speed delay testing. [Citation Graph (, )][DBLP]


  31. A Scan-Based Delay Test Method for Reduction of Overtesting. [Citation Graph (, )][DBLP]


  32. Static Crosstalk Noise Analysis with Transition Map. [Citation Graph (, )][DBLP]


  33. A Case Study on At-Speed Testing for a Gigahertz Microprocessor. [Citation Graph (, )][DBLP]


  34. Small Delay Fault Simulation for Sequential Circuits. [Citation Graph (, )][DBLP]


  35. Impact of Hazards on Pattern Selection for Small Delay Defects. [Citation Graph (, )][DBLP]


  36. A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. [Citation Graph (, )][DBLP]


  37. Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. [Citation Graph (, )][DBLP]


  38. Multiple Coupling Effects Oriented Path Delay Test Generation. [Citation Graph (, )][DBLP]


  39. Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. [Citation Graph (, )][DBLP]


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