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Publications of Author

1. Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, David Jensen
   Fast and efficient voltage scheduling by evolutionary slack distribution. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:659-662 [Conf]
   
2. Bita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski
   Designing a custom architecture for DCT using NISC technology. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:116-117 [Conf]
   
3. Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt
   An efficient retargetable framework for instruction-set simulation. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2003, pp:13-18 [Conf]
   
4. Mehrdad Reshadi, Daniel Gajski
   A cycle-accurate compilation algorithm for custom pipelined datapaths. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2005, pp:21-26 [Conf]
   
5. Mehrdad Reshadi, Prabhat Mishra
   Memory access optimizations in instruction-set simulators. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2005, pp:237-242 [Conf]
   
6. Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski
   Generic netlist representation for system and PE level design exploration. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2006, pp:282-287 [Conf]
   
7. Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt
   Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:758-763 [Conf]
   
8. Mehrdad Reshadi, Nikil D. Dutt
   Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:786-791 [Conf]
   
9. Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski
   A Graph Based Algorithm for Data Path Optimization in Custom Processors. [Citation Graph (0, 0)][DBLP]
   DSD, 2006, pp:496-503 [Conf]
   
10. Mehrdad Reshadi, Nikil D. Dutt
    Reducing Compilation Time Overhead in Compiled Simulators. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:151-0 [Conf]
    
11. Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski
    Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:69-76 [Conf]
    
12. Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta
    Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:261-266 [Conf]
    
13. Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra
    A retargetable framework for instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:431-452 [Journal]
    
14. Mehrdad Reshadi, Daniel Gajski
    Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1337-1342 [Conf]
    
15. Mehrdad Reshadi, Nikil Dutt
    Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
16. 
    C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). [Citation Graph (, )][DBLP]
    
    
17. 
    Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . [Citation Graph (, )][DBLP]