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## Search the dblp DataBase
Aarti Gupta:
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## Publications of Author- Aarti Gupta, Albert E. Casavant, Pranav Ashar, Akira Mukaiyama, Kazutoshi Wakabayashi, X. G. Liu
**Property-Specific Testbench Generation for Guided Simulation.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:524-534 [Conf] - Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta
**Whodunit? Causal Analysis for Counterexamples.**[Citation Graph (0, 0)][DBLP] ATVA, 2006, pp:82-95 [Conf] - Malay K. Ganai, Aarti Gupta, Pranav Ashar
**Efficient Modeling of Embedded Memories in Bounded Model Checking.**[Citation Graph (0, 0)][DBLP] CAV, 2004, pp:440-452 [Conf] - Aarti Gupta, Allan L. Fisher
**Parametric Circuit Representation Using Inductive Boolean Functions.**[Citation Graph (0, 0)][DBLP] CAV, 1993, pp:15-28 [Conf] - Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar
**Abstraction and BDDs Complement SAT-Based BMC in DiVer.**[Citation Graph (0, 0)][DBLP] CAV, 2003, pp:206-209 [Conf] - Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar
**F-Soft: Software Verification Platform.**[Citation Graph (0, 0)][DBLP] CAV, 2005, pp:301-306 [Conf] - Himanshu Jain, Franjo Ivancic, Aarti Gupta, Ilya Shlyakhter, Chao Wang
**Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop.**[Citation Graph (0, 0)][DBLP] CAV, 2006, pp:137-151 [Conf] - Vineet Kahlon, Aarti Gupta, Nishant Sinha
**Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions.**[Citation Graph (0, 0)][DBLP] CAV, 2006, pp:286-299 [Conf] - Vineet Kahlon, Franjo Ivancic, Aarti Gupta
**Reasoning About Threads Communicating via Locks.**[Citation Graph (0, 0)][DBLP] CAV, 2005, pp:505-518 [Conf] - Daijue Tang, Sharad Malik, Aarti Gupta, C. Norris Ip
**Symmetry Reduction in SAT-Based Model Checking.**[Citation Graph (0, 0)][DBLP] CAV, 2005, pp:125-138 [Conf] - Aarti Gupta, Pranav Ashar, Sharad Malik
**Exploiting Retiming in a Guided Simulation Based Validation Methodology.**[Citation Graph (0, 0)][DBLP] CHARME, 1999, pp:350-353 [Conf] - Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar
**Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking.**[Citation Graph (0, 0)][DBLP] CHARME, 2003, pp:334-347 [Conf] - Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik
**Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:747-750 [Conf] - Malay K. Ganai, Aarti Gupta, Pranav Ashar
**Beyond safety: customized SAT-based model checking.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:738-743 [Conf] - Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar
**Learning from BDDs in SAT-based bounded model checking.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:824-829 [Conf] - Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar
**Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:536-541 [Conf] - Aarti Gupta, Sharad Malik, Pranav Ashar
**Toward Formalizing a Validation Methodology Using Simulation Coverage.**[Citation Graph (0, 0)][DBLP] DAC, 1997, pp:740-745 [Conf] - Chao Wang, Aarti Gupta, Malay K. Ganai
**Predicate learning and selective theory deduction for a difference logic solver.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:235-240 [Conf] - Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar
**Property-specific witness graph generation for guided simulation.**[Citation Graph (0, 0)][DBLP] DATE, 2001, pp:799- [Conf] - Malay K. Ganai, Aarti Gupta, Pranav Ashar
**Verification of Embedded Memory Systems using Efficient Memory Modeling.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:1096-1101 [Conf] - Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta
**Disjunctive image computation for embedded software verification.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:1205-1210 [Conf] - Moon-Jung Chung, Edward J. Toy, Aarti Gupta
**A Parallel Computer Based on Cube-Connected Cycles for Wafer-Scale.**[Citation Graph (0, 0)][DBLP] FJCC, 1986, pp:325-334 [Conf] - Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta
**SAT-Based Image Computation with Application in Reachability Analysis.**[Citation Graph (0, 0)][DBLP] FMCAD, 2000, pp:354-371 [Conf] - Pranav Ashar, Aarti Gupta, Sharad Malik
**Using complete-1-distinguishability for FSM equivalence checking.**[Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:346-353 [Conf] - Malay K. Ganai, Aarti Gupta, Pranav Ashar
**Efficient SAT-based unbounded symbolic model checking using circuit cofactoring.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:510-517 [Conf] - Aarti Gupta, Allan L. Fisher
**Representation and symbolic manipulation of linearly inductive Boolean functions.**[Citation Graph (0, 0)][DBLP] ICCAD, 1993, pp:192-199 [Conf] - Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar
**Iterative Abstraction using SAT-based BMC with Proof Analysis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:416-423 [Conf] - Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik
**Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs.**[Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:286-292 [Conf] - Malay K. Ganai, Aarti Gupta
**Accelerating high-level bounded model checking.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:794-801 [Conf] - Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya
**Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.**[Citation Graph (0, 0)][DBLP] ICCD, 1999, pp:458-466 [Conf] - Aarti Gupta, Allan L. Fisher
**Tradeoffs in Canonical Sequential Function Representations.**[Citation Graph (0, 0)][DBLP] ICCD, 1994, pp:111-116 [Conf] - Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai
**Model Checking C Programs Using F-SOFT.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:297-308 [Conf] - Aarti Gupta, Allan L. Fisher
**Flexible Parallel Polygon Rendering.**[Citation Graph (0, 0)][DBLP] ICPP (3), 1990, pp:87-91 [Conf] - Aarti Gupta, Tim Oates
**Using Ontologies and the Web to Learn Lexical Semantics.**[Citation Graph (0, 0)][DBLP] IJCAI, 2007, pp:1618-1623 [Conf] - Vineet Kahlon, Aarti Gupta
**An Automata-Theoretic Approach for Model Checking Threads for LTL Propert.**[Citation Graph (0, 0)][DBLP] LICS, 2006, pp:101-110 [Conf] - Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti Gupta
**Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination.**[Citation Graph (0, 0)][DBLP] LPAR, 2005, pp:322-336 [Conf] - Vineet Kahlon, Aarti Gupta
**On the analysis of interacting pushdown systems.**[Citation Graph (0, 0)][DBLP] POPL, 2007, pp:303-314 [Conf] - Sriram Sankaranarayanan, Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta
**Static Analysis in Disjunctive Numerical Domains.**[Citation Graph (0, 0)][DBLP] SAS, 2006, pp:3-17 [Conf] - Himanshu Jain, Franjo Ivancic, Aarti Gupta, Malay K. Ganai
**Localization and Register Sharing for Predicate Abstraction.**[Citation Graph (0, 0)][DBLP] TACAS, 2005, pp:397-412 [Conf] - Malay K. Ganai, Aarti Gupta, Pranav Ashar
[Citation Graph (0, 0)][DBLP]*DiVer*: SAT-Based Model Checking Platform for Verifying Large Scale Systems. TACAS, 2005, pp:575-580 [Conf] - Malay K. Ganai, Muralidhar Talupur, Aarti Gupta
[Citation Graph (0, 0)][DBLP]*SDSAT*: Tight Integration of*Small Domain Encoding*and*Lazy*Approaches in a Separation Logic Solver. TACAS, 2006, pp:135-150 [Conf] - Aarti Gupta, Pranav Ashar
**Fast Error Diagnosis for Combinational Verification.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:442-448 [Conf] - Aarti Gupta, Pranav Ashar
**Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1998, pp:222-225 [Conf] - Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi
**Property-Specific Testbench Generation for Guided Simulation.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:524-0 [Conf] - Aarti Gupta, Malay K. Ganai, Pranav Ashar
**Lazy Constraints and SAT Heuristics for Proof-Based Abstraction.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:183-188 [Conf] - Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi
**Synthesizing "Verification Aware" Models: Why and How?**[Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:50-56 [Conf] - Aarti Gupta
**Assertion-based verification turns the corner.**[Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2002, v:19, n:4, pp:131-132 [Journal] - Aarti Gupta
**Formal Hardware Verification Methods: A Survey.**[Citation Graph (0, 0)][DBLP] Formal Methods in System Design, 1992, v:1, n:2/3, pp:151-238 [Journal] - Mukul R. Prasad, Armin Biere, Aarti Gupta
**A survey of recent advances in SAT-based formal verification.**[Citation Graph (0, 0)][DBLP] STTT, 2005, v:7, n:2, pp:156-173 [Journal] - Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar
**Efficient distributed SAT and SAT-based distributed Bounded Model Checking.**[Citation Graph (0, 0)][DBLP] STTT, 2006, v:8, n:4-5, pp:387-396 [Journal] - Pranav Ashar, Aarti Gupta, Sharad Malik
**Using complete-1-distinguishability for FSM equivalence checking.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:569-590 [Journal] - Chao Wang, Zijiang Yang, Aarti Gupta, Franjo Ivancic
**Using Counterexamples for Improving the Precision of Reachability Computation with Polyhedra.**[Citation Graph (0, 0)][DBLP] CAV, 2007, pp:352-365 [Conf] - Vineet Kahlon, Yu Yang, Sriram Sankaranarayanan, Aarti Gupta
**Fast and Accurate Static Data-Race Detection for Concurrent Programs.**[Citation Graph (0, 0)][DBLP] CAV, 2007, pp:226-239 [Conf] - Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic
**Mixed symbolic representations for model checking software programs.**[Citation Graph (0, 0)][DBLP] MEMOCODE, 2006, pp:17-26 [Conf] - Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta
**Program Analysis Using Symbolic Ranges.**[Citation Graph (0, 0)][DBLP] SAS, 2007, pp:366-383 [Conf] - Aarti Gupta, Malay K. Ganai, Chao Wang
**SAT-Based Verification Methods and Applications in Hardware Verification.**[Citation Graph (0, 0)][DBLP] SFM, 2006, pp:108-143 [Conf] - Malay K. Ganai, Aarti Gupta, Pranav Ashar
**Verification of Embedded Memory Systems using Efficient Memory Modeling**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] - Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta
**Disjunctive image computation for software verification.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal] **Efficient BMC for Multi-Clock Systems with Clocked Specifications.**[Citation Graph (, )][DBLP]**Dynamic Model Checking with Property Driven Pruning to Detect Race Conditions.**[Citation Graph (, )][DBLP]**Software Verification: Roles and Challenges for Automatic Decision Procedures.**[Citation Graph (, )][DBLP]**Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique.**[Citation Graph (, )][DBLP]**Tunneling and slicing: towards scalable BMC.**[Citation Graph (, )][DBLP]**Completeness in SMT-based BMC for Software Programs.**[Citation Graph (, )][DBLP]**Refining the control structure of loops using static analysis.**[Citation Graph (, )][DBLP]**Symbolic Predictive Analysis for Concurrent Programs.**[Citation Graph (, )][DBLP]**Induction in CEGAR for Detecting Counterexamples.**[Citation Graph (, )][DBLP]**From Hardware Verification to Software Verification: Re-use and Re-learn.**[Citation Graph (, )][DBLP]**Monte-carlo techniques for falsification of temporal properties of non-linear hybrid systems.**[Citation Graph (, )][DBLP]**Hybrid CEGAR: combining variable hiding and predicate abstraction.**[Citation Graph (, )][DBLP]**Mining library specifications using inductive logic programming.**[Citation Graph (, )][DBLP]**Efficient SAT-based Bounded Model Checking for Software Verification.**[Citation Graph (, )][DBLP]**Dynamic inference of likely data preconditions over predicates by tree learning.**[Citation Graph (, )][DBLP]**Program analysis via satisfiability modulo path programs.**[Citation Graph (, )][DBLP]**Robustness of Model-Based Simulations.**[Citation Graph (, )][DBLP]**SLR: Path-Sensitive Analysis through Infeasible-Path Detection and Syntactic Language Refinement.**[Citation Graph (, )][DBLP]**Symbolic pruning of concurrent program executions.**[Citation Graph (, )][DBLP]**Modular verification of web services using efficient symbolic encoding and summarization.**[Citation Graph (, )][DBLP]**Efficient Modeling of Concurrent Systems in BMC.**[Citation Graph (, )][DBLP]**Peephole Partial Order Reduction.**[Citation Graph (, )][DBLP]**Trace-Based Symbolic Analysis for Atomicity Violations.**[Citation Graph (, )][DBLP]**Semantic Reduction of Thread Interleavings in Concurrent Programs.**[Citation Graph (, )][DBLP]**Model Checking Concurrent Programs.**[Citation Graph (, )][DBLP]
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