|
Search the dblp DataBase
Albert E. Casavant:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Aarti Gupta, Albert E. Casavant, Pranav Ashar, Akira Mukaiyama, Kazutoshi Wakabayashi, X. G. Liu
Property-Specific Testbench Generation for Guided Simulation. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:524-534 [Conf]
- Albert E. Casavant
MIST - A Design Aid for Programmable Pipelined Processors. [Citation Graph (0, 0)][DBLP] DAC, 1994, pp:532-536 [Conf]
- Kristen N. McNall, Albert E. Casavant
Automatic Operator Configuration in the Synthesis of Pipelined Architectures. [Citation Graph (0, 0)][DBLP] DAC, 1990, pp:174-179 [Conf]
- Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar
Property-specific witness graph generation for guided simulation. [Citation Graph (0, 0)][DBLP] DATE, 2001, pp:799- [Conf]
- Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi
Property-Specific Testbench Generation for Guided Simulation. [Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:524-0 [Conf]
- Ti-Yen Yen, Alex Ishii, Albert E. Casavant, Wayne Wolf
Efficient Algorithms for Interface Timing Verification. [Citation Graph (0, 0)][DBLP] Formal Methods in System Design, 1998, v:12, n:3, pp:241-265 [Journal]
- Richard I. Hartley, Albert E. Casavant
Optimizing pipelined networks of associative and commutative operators. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:11, pp:1418-1425 [Journal]
Efficient algorithms for interface timing verification. [Citation Graph (, )][DBLP]
Search in 0.001secs, Finished in 0.002secs
|