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Pranav Ashar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Aarti Gupta, Albert E. Casavant, Pranav Ashar, Akira Mukaiyama, Kazutoshi Wakabayashi, X. G. Liu
    Property-Specific Testbench Generation for Guided Simulation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:524-534 [Conf]
  2. Malay K. Ganai, Aarti Gupta, Pranav Ashar
    Efficient Modeling of Embedded Memories in Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2004, pp:440-452 [Conf]
  3. Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar
    Abstraction and BDDs Complement SAT-Based BMC in DiVer. [Citation Graph (0, 0)][DBLP]
    CAV, 2003, pp:206-209 [Conf]
  4. Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar
    F-Soft: Software Verification Platform. [Citation Graph (0, 0)][DBLP]
    CAV, 2005, pp:301-306 [Conf]
  5. Aarti Gupta, Pranav Ashar, Sharad Malik
    Exploiting Retiming in a Guided Simulation Based Validation Methodology. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:350-353 [Conf]
  6. Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar
    Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 2003, pp:334-347 [Conf]
  7. Pranav Ashar, Srinivas Devadas, A. Richard Newton
    A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:601-606 [Conf]
  8. Pranav Ashar, Sharad Malik
    Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:77-80 [Conf]
  9. Srihari Cadambi, Chandra Mulpuri, Pranav Ashar
    A fast, inexpensive and scalable hardware acceleration technique for functional simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:570-575 [Conf]
  10. Farzan Fallah, Pranav Ashar, Srinivas Devadas
    Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:666-671 [Conf]
  11. Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik
    Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:747-750 [Conf]
  12. Malay K. Ganai, Aarti Gupta, Pranav Ashar
    Beyond safety: customized SAT-based model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:738-743 [Conf]
  13. Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar
    Learning from BDDs in SAT-based bounded model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:824-829 [Conf]
  14. Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar
    Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:536-541 [Conf]
  15. Aarti Gupta, Sharad Malik, Pranav Ashar
    Toward Formalizing a Validation Methodology Using Simulation Coverage. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:740-745 [Conf]
  16. José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar
    Scheduling Techniques to Enable Power Management. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:349-352 [Conf]
  17. Vivek Tiwari, Pranav Ashar, Sharad Malik
    Technology Mapping for Lower Power. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:74-79 [Conf]
  18. Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi
    Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:194-199 [Conf]
  19. Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar
    Property-specific witness graph generation for guided simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:799- [Conf]
  20. Malay K. Ganai, Aarti Gupta, Pranav Ashar
    Verification of Embedded Memory Systems using Efficient Memory Modeling. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1096-1101 [Conf]
  21. Zhen Luo, Margaret Martonosi, Pranav Ashar
    An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:158-167 [Conf]
  22. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Accelerating Boolean Satisfiability with Configurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:186-195 [Conf]
  23. Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta
    SAT-Based Image Computation with Application in Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:354-371 [Conf]
  24. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Solving Boolean Satisfiability with Dynamic Hardware Configurations. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:326-335 [Conf]
  25. Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama
    Verification of RTL generated from scheduled behavior in a high-level synthesis flow. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:517-524 [Conf]
  26. Pranav Ashar, Matthew Cheong
    Efficient breadth-first manipulation of binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:622-627 [Conf]
  27. Pranav Ashar, Sujit Dey, Sharad Malik
    Exploiting multi-cycle false paths in the performance optimization of sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:510-517 [Conf]
  28. Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:84-87 [Conf]
  29. Pranav Ashar, Aarti Gupta, Sharad Malik
    Using complete-1-distinguishability for FSM equivalence checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:346-353 [Conf]
  30. Pranav Ashar, Sharad Malik
    Fast functional simulation using branching programs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:408-412 [Conf]
  31. Malay K. Ganai, Aarti Gupta, Pranav Ashar
    Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:510-517 [Conf]
  32. Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar
    Iterative Abstraction using SAT-based BMC with Proof Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:416-423 [Conf]
  33. Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik
    Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:286-292 [Conf]
  34. Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya
    Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:458-466 [Conf]
  35. Pranav Ashar, Abhijit Ghosh, Srinivas Devadas
    Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:259-264 [Conf]
  36. Vivek Tiwari, Sharad Malik, Pranav Ashar
    Guarded evaluation: pushing power management to logic synthesis/design. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:221-226 [Conf]
  37. Pranav Ashar, Srinivas Devadas, Kurt Keutzer
    Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:887-896 [Conf]
  38. Malay K. Ganai, Aarti Gupta, Pranav Ashar
    DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems. [Citation Graph (0, 0)][DBLP]
    TACAS, 2005, pp:575-580 [Conf]
  39. Aarti Gupta, Pranav Ashar
    Fast Error Diagnosis for Combinational Verification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:442-448 [Conf]
  40. Aarti Gupta, Pranav Ashar
    Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:222-225 [Conf]
  41. Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi
    Property-Specific Testbench Generation for Guided Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:524-0 [Conf]
  42. Aarti Gupta, Malay K. Ganai, Pranav Ashar
    Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:183-188 [Conf]
  43. Anand Raghunathan, Pranav Ashar, Sharad Malik
    Test generation for cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:104-109 [Conf]
  44. Yang Xia, Pranav Ashar
    Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:449-0 [Conf]
  45. Pranav Ashar, Srinivas Devadas, Kurt Keutzer
    Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1993, v:2, n:1, pp:93-112 [Journal]
  46. Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar
    Efficient distributed SAT and SAT-based distributed Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    STTT, 2006, v:8, n:4-5, pp:387-396 [Journal]
  47. Pranav Ashar, Sujit Dey, Sharad Malik
    Exploiting multicycle false paths in the performance optimization of sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1067-1075 [Journal]
  48. Pranav Ashar, Srinivas Devadas, A. Richard Newton
    Optimum and heuristic algorithms for an approach to finite state machine decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:296-310 [Journal]
  49. Pranav Ashar, Srinivas Devadas, A. Richard Newton
    Irredundant interacting sequential machines via optimal logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:311-325 [Journal]
  50. Pranav Ashar, Sharad Malik
    Functional timing analysis using ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1025-1030 [Journal]
  51. Anand Raghunathan, Pranav Ashar, Sharad Malik
    Test generation for cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1408-1414 [Journal]
  52. Vivek Tiwari, Sharad Malik, Pranav Ashar
    Guarded evaluation: pushing power management to logic synthesis/design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1051-1060 [Journal]
  53. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Using configurable computing to accelerate Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:861-868 [Journal]
  54. Pranav Ashar, Aarti Gupta, Sharad Malik
    Using complete-1-distinguishability for FSM equivalence checking. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:569-590 [Journal]
  55. Malay K. Ganai, Aarti Gupta, Pranav Ashar
    Verification of Embedded Memory Systems using Efficient Memory Modeling [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  56. Farzan Fallah, Pranav Ashar, Srinivas Devadas
    Functional vector generation for sequential HDL models under an observability-based code coverage metric. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:919-923 [Journal]

  57. Efficient SAT-based Bounded Model Checking for Software Verification. [Citation Graph (, )][DBLP]


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