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Puneet Gupta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
    Detailed placement for improved depth of focus and CD control. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:343-348 [Conf]
  2. Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    Toward a methodology for manufacturability-driven design rule exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:311-316 [Conf]
  3. Yu Chen, Puneet Gupta, Andrew B. Kahng
    Performance-impact limited area fill synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:22-27 [Conf]
  4. Puneet Gupta, Fook-Luen Heng
    Toward a systematic-variation aware timing methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:321-326 [Conf]
  5. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
    Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:365-368 [Conf]
  6. Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
    Selective gate-length biasing for cost-effective runtime leakage control. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:327-330 [Conf]
  7. Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:16-21 [Conf]
  8. Saumil Shah, Puneet Gupta, Andrew B. Kahng
    Standard cell library optimization for leakage reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:983-986 [Conf]
  9. Puneet Gupta, Andrew B. Kahng
    Manufacturing-Aware Physical Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:681-688 [Conf]
  10. Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
    Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:754-759 [Conf]
  11. Puneet Gupta, David S. Doermann, Daniel DeMenthon
    Beam Search for Feature Selection in Automatic SVM Defect Classification. [Citation Graph (0, 0)][DBLP]
    ICPR (2), 2002, pp:212-215 [Conf]
  12. Puneet Gupta, Andrew B. Kahng
    Quantifying Error in Dynamic Power Estimation of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:273-278 [Conf]
  13. Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
    A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:339-343 [Conf]
  14. Puneet Gupta, Andrew B. Kahng, Puneet Sharma
    A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:421-426 [Conf]
  15. Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    Performance Driven OPC for Mask Cost Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:270-275 [Conf]
  16. Puneet Gupta, Michael S. Hsiao
    High Quality ATPG for Delay Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:584-591 [Conf]
  17. Puneet Gupta, Michael S. Hsiao
    ALAPTF: A new Transition Faultmodel and the ATPG Algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1053-1060 [Conf]
  18. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
    Investigation of performance metrics for interconnect stack architectures. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:23-29 [Conf]
  19. Puneet Gupta, Andrew B. Kahng
    Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:431-436 [Conf]
  20. Puneet Gupta, Andrew B. Kahng
    Efficient Design and Analysis of Robust Power Distribution Meshes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:337-342 [Conf]
  21. Russell H. Taylor, Patrick S. Jensen, Louis L. Whitcomb, Aaron C. Barnes, Rajesh Kumar, Dan Stoianovici, Puneet Gupta, Zhengxian Wang, Eugene de Dejuan, Louis R. Kavoussi
    A Steady-Hand Robotic System for Microsurgical Augmentation. [Citation Graph (0, 0)][DBLP]
    I. J. Robotic Res., 1999, v:18, n:12, pp:1201-1210 [Journal]
  22. Puneet Gupta, Deependra Moitra
    Evolving a pervasive IT infrastructure: a technology integration approach. [Citation Graph (0, 0)][DBLP]
    Personal and Ubiquitous Computing, 2004, v:8, n:1, pp:31-41 [Journal]
  23. Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
    Layout-aware scan chain synthesis for improved path delay fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1104-1114 [Journal]
  24. Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
    Gate-length biasing for runtime-leakage control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1475-1485 [Journal]
  25. Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
    Routing-aware scan chain ordering. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:546-560 [Journal]
  26. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester
    Line-End Shortening is Not Always a Failure. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:270-271 [Conf]

  27. Prioritized Buffer Management Policy for Wireless Sensor Nodes. [Citation Graph (, )][DBLP]


  28. Investigation of diffusion rounding for post-lithography analysis. [Citation Graph (, )][DBLP]


  29. Accounting for non-linear dependence using function driven component analysis. [Citation Graph (, )][DBLP]


  30. On the futility of statistical power optimization. [Citation Graph (, )][DBLP]


  31. Experimental analysis of RSSI-based location estimation in wireless sensor networks. [Citation Graph (, )][DBLP]


  32. mConnect: A context aware mobile transaction middleware. [Citation Graph (, )][DBLP]


  33. Bounded-lifetime integrated circuits. [Citation Graph (, )][DBLP]


  34. Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. [Citation Graph (, )][DBLP]


  35. Eyecharts: constructive benchmarking of gate sizing heuristics. [Citation Graph (, )][DBLP]


  36. Software adaptation in quality sensitive applications to deal with hardware variability. [Citation Graph (, )][DBLP]


  37. Challenges at 45nm and beyond. [Citation Graph (, )][DBLP]


  38. A framework for early and systematic evaluation of design rules. [Citation Graph (, )][DBLP]


  39. Variation-aware speed binning of multi-core processors. [Citation Graph (, )][DBLP]


  40. Verification of Security Policy Enforcement in Enterprise Systems. [Citation Graph (, )][DBLP]


  41. Electrical Modeling of Lithographic Imperfections. [Citation Graph (, )][DBLP]


  42. On Electrical Modeling of Imperfect Diffusion Patterning. [Citation Graph (, )][DBLP]


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