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Publications of Author

1. Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man
   Virtual Java/FPGA interface for networked reconfiguration. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:558-563 [Conf]
   
2. Yu Pu, Yajun Ha
   An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:886-891 [Conf]
   
3. Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha
   Global Analysis of Resource Arbitration for MPSoC. [Citation Graph (0, 0)][DBLP]
   DSD, 2006, pp:71-78 [Conf]
   
4. Shakith Fernando, Ha Yajun
   Design of Networked Reconfigurable Encryption Engine. [Citation Graph (0, 0)][DBLP]
   FCCM, 2005, pp:285-286 [Conf]
   
5. Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man
   Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:1135-1138 [Conf]
   
6. Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man
   Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. [Citation Graph (0, 0)][DBLP]
   FPL, 2001, pp:264-274 [Conf]
   
7. Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Hugo De Man
   Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2000, pp:- [Conf]
   
8. Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man
   A Hardware Virtual Machine for the Networked Reconfiguration. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2000, pp:194-199 [Conf]
   
9. Yung Han Tan, Arun Krishnan Thampi, Daley Joseph Sebastian, Yajun Ha
   Design of Seamless Protocol Switching Layer for Voice Over Internet Protocol (Voip) That Switches Between Bluetooth and Ieee 802.11. [Citation Graph (0, 0)][DBLP]
   International Journal of Software Engineering and Knowledge Engineering, 2005, v:15, n:2, pp:271-278 [Journal]
   
10. Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Rudy Lauwereins, Hugo De Man
    Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2002, v:21, n:2, pp:131-144 [Journal]
    
11. Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha
    A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:726-731 [Conf]
    
12. 
    An optimized design for serial-parallel finite field multiplication over GF(2^m) based on all-one polynomials. [Citation Graph (, )][DBLP]
    
    
13. 
    Statistical noise margin estimation for sub-threshold combinational circuits. [Citation Graph (, )][DBLP]
    
    
14. 
    Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems. [Citation Graph (, )][DBLP]
    
    
15. 
    Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems. [Citation Graph (, )][DBLP]
    
    
16. 
    A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study. [Citation Graph (, )][DBLP]
    
    
17. 
    Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip. [Citation Graph (, )][DBLP]
    
    
18. 
    An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects. [Citation Graph (, )][DBLP]
    
    
19. 
    Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. [Citation Graph (, )][DBLP]
    
    
20. 
    Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. [Citation Graph (, )][DBLP]
    
    
21. 
    A low overhead fault tolerant FPGA with new connection box. [Citation Graph (, )][DBLP]
    
    
22. 
    An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects. [Citation Graph (, )][DBLP]
    
    
23. 
    Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA. [Citation Graph (, )][DBLP]
    
    
24. 
    sFPGA - A scalable switch based FPGA architecture and design methodology. [Citation Graph (, )][DBLP]
    
    
25. 
    sFPGA2 - A scalable GALS FPGA architecture and design methodology. [Citation Graph (, )][DBLP]
    
    
26. 
    V_t balancing and device sizing towards high yield of sub-threshold static logic gates. [Citation Graph (, )][DBLP]