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Serge Vernalde: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man
    Virtual Java/FPGA interface for networked reconfiguration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:558-563 [Conf]
  2. Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Ivo Bolsens
    Hardware/software partitioning of embedded system in OCAPI-xl. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:30-35 [Conf]
  3. E. Berrebi, Polen Kission, Serge Vernalde, S. De Troch, J. C. Herluison, J. Fréhel, Ahmed Amine Jerraya, Ivo Bolsens
    Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:573-578 [Conf]
  4. Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde
    Operating-system controlled network on chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:256-259 [Conf]
  5. Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels
    A 10 Mbit/s Upstream Cable Modem with Automatic equalization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:337-340 [Conf]
  6. Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels, Ivo Bolsens
    Hardware Reuse at the Behavioral Level. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:784-789 [Conf]
  7. Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens
    A Programming Environment for the Design of Complex High Speed ASICs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:315-320 [Conf]
  8. Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Ivo Bolsens
    A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:271-0 [Conf]
  9. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins
    Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1224-1229 [Conf]
  10. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
    Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10296-10301 [Conf]
  11. Jean-Yves Mignolet, Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
    Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10986-10993 [Conf]
  12. Robert Pasko, Serge Vernalde, Patrick Schaumont
    Techniques to Evolve a C++ Based System Design Language. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:302-309 [Conf]
  13. Vincent Nollet, Jean-Yves Mignolet, Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
    Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:81-87 [Conf]
  14. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
    Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:156-162 [Conf]
  15. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
    Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:278-279 [Conf]
  16. Andrei Bartic, Dirk Desmet, Jean-Yves Mignolet, Théodore Marescaux, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, J. Miller, Frédéric Robert
    Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:637-647 [Conf]
  17. Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man
    Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1135-1138 [Conf]
  18. Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man
    Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:264-274 [Conf]
  19. Théodore Marescaux, Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
    Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:795-805 [Conf]
  20. Théodore Marescaux, Jean-Yves Mignolet, Andrei Bartic, W. Moffat, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
    Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:595-605 [Conf]
  21. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
    ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:61-70 [Conf]
  22. Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor
    Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:585-594 [Conf]
  23. Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
    Designing an Operating System for a Heterogeneous Reconfigurable So. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:174- [Conf]
  24. Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Hugo De Man
    Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  25. Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man
    A Hardware Virtual Machine for the Networked Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:194-199 [Conf]
  26. Patrick Schaumont, Geert Vanmeerbeeck, E. Watzeels, Serge Vernalde, Marc Engels, Ivo Bolsens
    A Technique for Combined Virtual Prototyping and Hardware Design. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:156-161 [Conf]
  27. Richard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor
    Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:313-328 [Conf]
  28. Théodore Marescaux, Vincent Nollet, Jean-Yves Mignolet, Andrei Bartic, W. Moffat, Prabhat Avasare, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
    Run-time support for heterogeneous multitasking on reconfigurable SoCs. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:107-130 [Journal]
  29. Robert Pasko, Patrick Schaumont, Veerle Derudder, Serge Vernalde, Daniela Durackova
    A new algorithm for elimination of common subexpressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:58-68 [Journal]
  30. Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Rudy Lauwereins, Hugo De Man
    Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2002, v:21, n:2, pp:131-144 [Journal]
  31. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
    A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:291-301 [Journal]

  32. Highly scalable parallel parametrizable architecture of the motion estimator. [Citation Graph (, )][DBLP]


  33. Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications. [Citation Graph (, )][DBLP]


  34. ASIC synthesis of a flexible 80 Mbit/s Reed-Solomon Codec. [Citation Graph (, )][DBLP]


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