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Publications of Author

1. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
   Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:645-648 [Conf]
   
2. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
   Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. [Citation Graph (0, 0)][DBLP]
   CASES, 2000, pp:85-93 [Conf]
   
3. Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee
   Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:722-728 [Conf]
   
4. Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee
   Accurate Area and Delay Estimators for FPGAs. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:862-869 [Conf]
   
5. Prithviraj Banerjee, Debabrata Bagchi, Malay Haldar, Anshuman Nayak, Victor Kim, R. Uribe
   Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. [Citation Graph (0, 0)][DBLP]
   FCCM, 2003, pp:263-264 [Conf]
   
6. Prithviraj Banerjee, Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky
   A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
   FCCM, 2000, pp:39-48 [Conf]
   
7. Prithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson
   Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 2003, pp:237- [Conf]
   
8. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
   Parallel algorithms for FPGA placement. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2000, pp:86-94 [Conf]
   
9. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
   A System for Synthesizing Optimized FPGA Hardware from MATLAB. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2001, pp:314-319 [Conf]
   
10. Malay Haldar, Anshuman Nayak, Abhay Kanhere, Pramod G. Joisha, Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee
    Match Virtual Machine: An Adaptive Runtime System to Execute MATLAB in Parallel. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:145-152 [Conf]
    
11. Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi
    A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs. [Citation Graph (0, 0)][DBLP]
    IWDC, 2002, pp:246-256 [Conf]
    
12. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee, Nagaraj Shenoy
    Fpga Hardware Synthesis From Matlab. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:299-304 [Conf]
    
13. Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, R. Anderson, J. R. Uribe
    Overview of a compiler for synthesizing MATLAB programs onto FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:312-324 [Journal]
    
14. 
    Construction of concrete verification models from C++. [Citation Graph (, )][DBLP]