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Ahmet T. Erdogan :
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Wei Han , Ahmet T. Erdogan , Tughrul Arslan , M. Hasan The development of high performance FFT IP cores through hybrid low power algorithmic methodology. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:549-552 [Conf ] Muhammad Akhtar Khan , Abdul Hameed , Ahmet T. Erdogan Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC). [Citation Graph (0, 0)][DBLP ] ERSA, 2006, pp:178-183 [Conf ] Yutian Zhao , Ahmet T. Erdogan , Tughrul Arslan A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications. [Citation Graph (0, 0)][DBLP ] IPDPS, 2005, pp:- [Conf ] Ahmet T. Erdogan , Tughrul Arslan Low power block based FIR filtering cores. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:341-344 [Conf ] Yao Gang , Tughrul Arslan , Ahmet T. Erdogan An efficient pre-traceback approach for Viterbi decoding in wireless communication. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 2005, pp:5441-5444 [Conf ] Wei Han , Ahmet T. Erdogan , Tughrul Arslan , M. Hasan Low power commutator for pipelined FFT processors. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2005, pp:5274-5277 [Conf ] Yutian Zhao , Ahmet T. Erdogan , Tughrul Arslan A novel low-power reconfigurable FFT processor. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2005, pp:41-44 [Conf ] Jichuan Zhao , Ahmet T. Erdogan , Tughrul Arslan A novel application specific network protocol for wireless sensor networks. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 2005, pp:5894-5897 [Conf ] A. C. McCormick , P. M. Grant , John S. Thompson , Tughrul Arslan , Ahmet T. Erdogan A low power MMSE receiver architecture for multi-carrier CDMA. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2001, pp:41-44 [Conf ] Ahmet T. Erdogan , Tughrul Arslan A coefficient segmentation algorithm for low power implementation of FIR filters. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 1999, pp:359-362 [Conf ] Tughrul Arslan , Ahmet T. Erdogan Low power implementation of high throughput FIR filters. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2002, pp:373-376 [Conf ] Ahmet T. Erdogan , Tughrul Arslan Low Power FIR Filter Implementations Based on Coefficient Ordering Algorithm. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2004, pp:226-228 [Conf ] J. H. Han , Ahmet T. Erdogan , Tughrul Arslan High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2005, pp:173-178 [Conf ] Kristian Hildingsson , Tughrul Arslan , Ahmet T. Erdogan Energy Evaluation Methodology for Platform Based System-on-Chip Design. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2004, pp:61-68 [Conf ] Zahid Khan , John S. Thompson , Tughrul Arslan , Ahmet T. Erdogan Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2006, pp:12-17 [Conf ] T. Takahashi , Ahmet T. Erdogan , Tughrul Arslan , J. H. Han Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2006, pp:444-445 [Conf ] J. H. Han , Ahmet T. Erdogan , Tughrul Arslan A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication Systems. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2006, pp:185-192 [Conf ] Ashwin K. Kumaraswamy , Ahmet T. Erdogan , Indrajit Atluri Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis. [Citation Graph (0, 0)][DBLP ] IWSOC, 2004, pp:193-197 [Conf ] Zahid Khan , Tughrul Arslan , Ahmet T. Erdogan A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses. [Citation Graph (0, 0)][DBLP ] PATMOS, 2004, pp:585-592 [Conf ] Zahid Khan , Tughrul Arslan , Ahmet T. Erdogan Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:314-317 [Conf ] Zahid Khan , Tughrul Arslan , Ahmet T. Erdogan A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2005, pp:751-756 [Conf ] Zahid Khan , Tughrul Arslan , John S. Thompson , Ahmet T. Erdogan Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:734-737 [Conf ] Mark P. Tennant , Ahmet T. Erdogan , Tughrul Arslan , John S. Thompson A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:263-268 [Conf ] C. H. Wang , Ahmet T. Erdogan , Tughrul Arslan Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2005, pp:659-662 [Conf ] J. H. Han , Ahmet T. Erdogan , Tughrul Arslan A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:756-762 [Conf ] Asral Bahari , Tughrul Arslan , Ahmet T. Erdogan Interframe Bus Encoding Technique for Low Power Video Compression. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:691-698 [Conf ] Zahid Khan , Tughrul Arslan , John S. Thompson , Ahmet T. Erdogan Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:744-749 [Conf ] Syamsiah Mashohor , Jonathan R. Evans , Ahmet T. Erdogan Automatic Hybrid Genetic Algorithm Based Printed Circuit Board Inspection. [Citation Graph (0, 0)][DBLP ] AHS, 2006, pp:390-400 [Conf ] Jichuan Zhao , Ahmet T. Erdogan A Novel Self-Organizing Hybrid Network Protocol for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP ] AHS, 2006, pp:412-419 [Conf ] Nasri Sulaiman , Ahmet T. Erdogan A Multi-Objective Genetic Algorithm for On-Chip Real-time Adaptation of a Multi-Carrier Based Telecommunications Receiver. [Citation Graph (0, 0)][DBLP ] AHS, 2006, pp:424-427 [Conf ] B. Ahmad , Ahmet T. Erdogan , Sami Khawam Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC. [Citation Graph (0, 0)][DBLP ] AHS, 2006, pp:405-411 [Conf ] Tughrul Arslan , Nakul Haridas , Erfu Yang , Ahmet T. Erdogan , Nick Barton , A. J. Walton , John S. Thompson , Adrian Stoica , T. Vladimirova , Klaus D. McDonald-Maier , W. G. J. Howells ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace-Based Monitoring and Diagnostics. [Citation Graph (0, 0)][DBLP ] AHS, 2006, pp:323-329 [Conf ] Nakul Haridas , Ahmet T. Erdogan , Tughrul Arslan , Mark Begbie Adaptive Micro-Antenna on Silicon Substrate. [Citation Graph (0, 0)][DBLP ] AHS, 2006, pp:43-50 [Conf ] Zahid Khan , Tughrul Arslan , John S. Thompson , Ahmet T. Erdogan A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1569-1574 [Conf ] Erfu Yang , Ahmet T. Erdogan , Tughrul Arslan , Nick Barton System-Level Modeling and Multi-objective Evolutionary Design of Pipelined FFT Processors for Wireless OFDM Receivers. [Citation Graph (0, 0)][DBLP ] ICES, 2007, pp:210-221 [Conf ] Nazish Aslam , Mark Milward , Ioannis Nousias , Tughrul Arslan , Ahmet T. Erdogan Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-7 [Conf ] Prakash Srinivasan , Ali Ahmadinia , Ahmet T. Erdogan , Tughrul Arslan Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:1875-1878 [Conf ] Asral Bahari , Tughrul Arslan , Ahmet T. Erdogan Low power variable block size motion estimation using pixel truncation. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:3663-3666 [Conf ] Zhenyu Liu , Tughrul Arslan , Ahmet T. Erdogan An embedded low power reconfigurable fabric for finite state machine operations. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Mark P. Tennant , Ahmet T. Erdogan , Tughrul Arslan , John S. Thompson A novel equaliser architecture with dynamic length optimisation. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Zahid Khan , Tughrul Arslan , John S. Thompson , Ahmet T. Erdogan Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1281-1286 [Journal ] A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications. [Citation Graph (, )][DBLP ] An ILP formulation for task mapping and scheduling on multi-core architectures. [Citation Graph (, )][DBLP ] Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture. [Citation Graph (, )][DBLP ] SystemC-based Custom Reconfigurable Cores for Wireless Applications. [Citation Graph (, )][DBLP ] Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems. [Citation Graph (, )][DBLP ] Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures. [Citation Graph (, )][DBLP ] The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures. [Citation Graph (, )][DBLP ] System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems. [Citation Graph (, )][DBLP ] Scalability of a Novel Shifting Balance Theory-Based Optimization Algorithm: A Comparative Study on a Cluster-Based Wireless Sensor Network. [Citation Graph (, )][DBLP ] Low Power Hardware Architecture for VBSME Using Pixel Truncation. [Citation Graph (, )][DBLP ] A Novel Sampling Scheme for Efficient Analog to Digital Conversion. [Citation Graph (, )][DBLP ] Multiobjective Optimal Design of MEMS-Based Reconfigurable and Evolvable Sensor Networks for Space Applications. [Citation Graph (, )][DBLP ] Multi-Frequency Antenna design for Space-based Reconfigurable Satellite Sensor Node. [Citation Graph (, )][DBLP ] High Performance Embedded Reconfigurable Concatenated Convolution- Puncturing Fabric for 802.16. [Citation Graph (, )][DBLP ] Fault tolerant cellular Genetic Algorithm. [Citation Graph (, )][DBLP ] A novel shifting balance theory-based approach to optimization of an energy-constrained modulation scheme for wireless sensor networks. [Citation Graph (, )][DBLP ] A distributed cellular GA based architecture for real time GPS attitude determination. [Citation Graph (, )][DBLP ] Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer. [Citation Graph (, )][DBLP ] A novel CMOS exponential approximation circuit. [Citation Graph (, )][DBLP ] OFDM symbol timing synchronization system on a Reconfigurable Instruction Cell Array. [Citation Graph (, )][DBLP ] Evaluation of contrast limited adaptive histogram equalization (CLAHE) enhancement on a FPGA. [Citation Graph (, )][DBLP ] Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication. [Citation Graph (, )][DBLP ] Low Computation and Memory Access for Variable Block Size Motion Estimation Using Pixel Truncation. [Citation Graph (, )][DBLP ] I2 S3 the Integrated Intelligent Secure Sensor Systems Project. [Citation Graph (, )][DBLP ] Multi-Objective Evolutionary Optimizations of a Space-Based Reconfigurable Sensor Network under Hard Constraints. [Citation Graph (, )][DBLP ] An Improved Particle Swarm Optimization Algorithm for Power-Efficient Wireless Sensor Networks. [Citation Graph (, )][DBLP ] The Re-emission Side Channel. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.455secs