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Tughrul Arslan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wei Han, Ahmet T. Erdogan, Tughrul Arslan, M. Hasan
    The development of high performance FFT IP cores through hybrid low power algorithmic methodology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:549-552 [Conf]
  2. Zhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lindsay
    A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:639-644 [Conf]
  3. Adeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioannis Nousias, Iain Lindsay
    An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1256-1259 [Conf]
  4. Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan
    Automatic synthesis and scheduling of multirate DSP algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:635-638 [Conf]
  5. Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay
    A domain specific reconfigurable Viterbi fabric for system-on-chip applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:916-919 [Conf]
  6. Sami Khawam, Sajid Baloch, Arjun Pai, Imran Ahmed, Nizamettin Aydin, Tughrul Arslan, Fred Westall
    Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1230-1235 [Conf]
  7. Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan, Iain Lindsay
    System-level scheduling on instruction cell based reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:381-386 [Conf]
  8. Nizamettin Aydin, Tughrul Arslan, David R. S. Cumming
    Power/Area Analysis and Optimization of a DS-SS receiver for an Integrated Sensor Microsystem. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:402-407 [Conf]
  9. Ben I. Hounsell, Tughrul Arslan
    Evolutionary Design And Adaptation Of Digital Filters Within An Embedded Fault Tolerant Hardware Platform . [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2001, pp:127-135 [Conf]
  10. Jonathan R. Evans, Tughrul Arslan
    The Implementation of an Evolvable Hardware System for Real Time Image Registration on a System-on-Chip Platform. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2002, pp:142-146 [Conf]
  11. Robert I. Graham, Tughrul Arslan
    Rule Evolution In Order Based Diagnostic Systems. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2001, pp:280-286 [Conf]
  12. Evangelos F. Stefatos, Tughrul Arslan
    An Efficient Fault-Tolerant VLSI Architecture Using Parallel Evolvable Hardware Technology. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:97-103 [Conf]
  13. Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson
    An EHW Architecture for the Design of Unconstrained Low-Power FIR Filters for Sensor Control Using Custom-Reconfigurable Technology. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2005, pp:147-153 [Conf]
  14. Adrian Stoica, Didier Keymeulen, Tughrul Arslan, Vu Duong, Ricardo Salem Zebulum, Ian Ferguson, Xin Guo
    Circuit Self-Recovery Experiments in Extreme Environments. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:142-145 [Conf]
  15. Nasri Sulaiman, Tughrul Arslan
    A Genetic Algorithm for the Optimisation of a Reconfigurable Pipelined FFT Processor. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:104-108 [Conf]
  16. Nasri Sulaiman, Tughrul Arslan
    A Multi-objective Genetic Algorithm for On-chip Real-time Optimisation of Word Length and Power Consumption in a Pipelined FFT Processor targeting a MC-CDMA Receiver. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2005, pp:154-159 [Conf]
  17. Robert Thomson, Tughrul Arslan
    Evolvable Hardware for the Generation of Sequential Filter Circuits. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2002, pp:17-25 [Conf]
  18. Robert Thomson, Tughrul Arslan
    The Evolutionary Design and Synthesis of Non-Linear Digital VLSI Systems. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2003, pp:125-134 [Conf]
  19. Lirong Tian, Tughrul Arslan
    An Evolutionary Power Management Algorithm for SoC Based EHWSystems. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2003, pp:117-124 [Conf]
  20. Jiangning Xu, Tughrul Arslan
    An EHW Architecture for Real-Time GPS Attitude Determination Based on Parallel Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2002, pp:133-141 [Conf]
  21. Sami Khawam, Tughrul Arslan, Fred Westall
    Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:293-295 [Conf]
  22. Sajid Baloch, Imran Ahmed, Tughrul Arslan, Adrian Stoica
    Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:618-621 [Conf]
  23. Sami Khawam, Tughrul Arslan, Fred Westall
    Domain-Specific Reconfigurable Array for Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1139-1144 [Conf]
  24. Ben I. Hounsell, Tughrul Arslan
    A Novel Evolvable Hardware Framework for the Evolution of High Performance Digital Circuits. [Citation Graph (0, 0)][DBLP]
    GECCO, 2000, pp:525-0 [Conf]
  25. Lirong Tian, Tughrul Arslan
    A Genetic Algorithm for Energy Efficient Device Scheduling in Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    GECCO, 2003, pp:1614-1615 [Conf]
  26. Imran Ahmed, Tughrul Arslan, Sajid Baloch, Ian Underwood, Robin Woodburn
    Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless Communication. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  27. Sajid Baloch, Imran Ahmed, Tughrul Arslan
    Domain-Specific Reconfigurable Array Targeting Discrete Wavelet Transform for System-on-Chip Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  28. Konstantinos Katsoulakis, Tughrul Arslan, Tony Kirkham, Sami Khawam
    A Low-Power Reconfigurable Datapath for Advanced Speech Coding Algorithms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  29. Sami Khawam, Tughrul Arslan, Fred Westall
    Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  30. Evangelos F. Stefatos, Wei Han, Tughrul Arslan, Robert Thomson
    Low-Power Reconfigurable VLSI Architecture for the Implementation of FIR Filters. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  31. Yutian Zhao, Ahmet T. Erdogan, Tughrul Arslan
    A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  32. Wing On Fung, Tughrul Arslan
    A stochastic multi-objective algorithm for the design of high performance reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  33. Ahmet T. Erdogan, Tughrul Arslan
    Low power block based FIR filtering cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:341-344 [Conf]
  34. Yao Gang, Tughrul Arslan, Ahmet T. Erdogan
    An efficient pre-traceback approach for Viterbi decoding in wireless communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5441-5444 [Conf]
  35. Wei Han, Ahmet T. Erdogan, Tughrul Arslan, M. Hasan
    Low power commutator for pipelined FFT processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5274-5277 [Conf]
  36. M. Hasan, Tughrul Arslan
    A triple port RAM based low power commutator architecture for a pipelined FFT processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:353-356 [Conf]
  37. Sami Khawam, Tughrul Arslan, Fred Westall
    Embedded reconfigurable array targeting motion estimation applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:760-763 [Conf]
  38. Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay
    Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabric. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1048-1050 [Conf]
  39. Yutian Zhao, Ahmet T. Erdogan, Tughrul Arslan
    A novel low-power reconfigurable FFT processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:41-44 [Conf]
  40. Jichuan Zhao, Ahmet T. Erdogan, Tughrul Arslan
    A novel application specific network protocol for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5894-5897 [Conf]
  41. A. C. McCormick, P. M. Grant, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan
    A low power MMSE receiver architecture for multi-carrier CDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:41-44 [Conf]
  42. Mark S. Bright, Tughrul Arslan
    Multi-objective design strategy for high-level low power design of DSP systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:80-83 [Conf]
  43. Ahmet T. Erdogan, Tughrul Arslan
    A coefficient segmentation algorithm for low power implementation of FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 1999, pp:359-362 [Conf]
  44. M. Hasan, Tughrul Arslan
    A coefficient memory addressing scheme for VLSI implementation of FFT processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:850-853 [Conf]
  45. Tughrul Arslan, Ahmet T. Erdogan
    Low power implementation of high throughput FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:373-376 [Conf]
  46. Sajid Baloch, Tughrul Arslan, Adrian Stoica
    Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:330-345 [Conf]
  47. Indrajit Atluri, Tughrul Arslan
    Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:215-217 [Conf]
  48. Ahmet T. Erdogan, Tughrul Arslan
    Low Power FIR Filter Implementations Based on Coefficient Ordering Algorithm. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:226-228 [Conf]
  49. J. H. Han, Ahmet T. Erdogan, Tughrul Arslan
    High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:173-178 [Conf]
  50. Kristian Hildingsson, Tughrul Arslan, Ahmet T. Erdogan
    Energy Evaluation Methodology for Platform Based System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:61-68 [Conf]
  51. Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson
    Autonomous Realization of Boeing/JPL Sensor Electronics based on Reconfigurable System-on-Chip Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:85-90 [Conf]
  52. Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan
    Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:12-17 [Conf]
  53. T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J. H. Han
    Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:444-445 [Conf]
  54. J. H. Han, Ahmet T. Erdogan, Tughrul Arslan
    A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:185-192 [Conf]
  55. Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
    A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:585-592 [Conf]
  56. Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
    Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:314-317 [Conf]
  57. Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
    A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:751-756 [Conf]
  58. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
    Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:734-737 [Conf]
  59. Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson
    Custom Reconfigurable Architecture for Autonomous Fault-Recovery of MEMS Vibratory Sensor Electronics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:725-728 [Conf]
  60. Mark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan, John S. Thompson
    A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:263-268 [Conf]
  61. C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
    Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:659-662 [Conf]
  62. J. H. Han, Ahmet T. Erdogan, Tughrul Arslan
    A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:756-762 [Conf]
  63. Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan
    Interframe Bus Encoding Technique for Low Power Video Compression. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:691-698 [Conf]
  64. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
    Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:744-749 [Conf]
  65. Ioannis Nousias, Tughrul Arslan
    Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC). [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:420-423 [Conf]
  66. Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson
    Towards the Integration of Drive Control Loop Electronics of the JPL/Boeing Gyroscope within an Autonomous Robust Custom-Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:207-214 [Conf]
  67. Tughrul Arslan, Nakul Haridas, Erfu Yang, Ahmet T. Erdogan, Nick Barton, A. J. Walton, John S. Thompson, Adrian Stoica, T. Vladimirova, Klaus D. McDonald-Maier, W. G. J. Howells
    ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace-Based Monitoring and Diagnostics. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:323-329 [Conf]
  68. Nizamettin Aydin, Tughrul Arslan
    Power Driven Reconfigurable Complex Continuous Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:109-113 [Conf]
  69. Sajid Baloch, Tughrul Arslan, Adrian Stoica
    Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:270-280 [Conf]
  70. Sajid Baloch, Tughrul Arslan, Adrian Stoica
    An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:292-295 [Conf]
  71. Wing On Fung, Tughrul Arslan, Sami Khawam
    Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:200-206 [Conf]
  72. Nakul Haridas, Ahmet T. Erdogan, Tughrul Arslan, Mark Begbie
    Adaptive Micro-Antenna on Silicon Substrate. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:43-50 [Conf]
  73. Lukás Sekanina, Tughrul Arslan
    Evolvable Components-From Theory to Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    Genetic Programming and Evolvable Machines, 2005, v:6, n:4, pp:461-462 [Journal]
  74. Ben I. Hounsell, Tughrul Arslan, Robert Thomson
    Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform. [Citation Graph (0, 0)][DBLP]
    Soft Comput., 2004, v:8, n:5, pp:307-317 [Journal]
  75. Mark S. Bright, Tughrul Arslan
    Synthesis of low-power DSP systems using a genetic algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2001, v:5, n:1, pp:27-40 [Journal]
  76. Nizamettin Aydin, Tughrul Arslan, David R. S. Cumming
    A direct-sequence spread-spectrum communication system for integrated sensor microsystems. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Information Technology in Biomedicine, 2005, v:9, n:1, pp:4-12 [Journal]
  77. Zahid Khan, Tughrul Arslan
    Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:349-354 [Conf]
  78. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
    A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1569-1574 [Conf]
  79. Imran Ahmed, Tughrul Arslan
    A Reconfigurable Viterbi Decoder for a Communication Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  80. Sajid Baloch, Tughrul Arslan, Adrian Stoica
    An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  81. Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson
    Integrating the Electronics of the Control-Loops of the JPL/Boeing Gyroscope Within an Evolvable Hardware Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  82. Erfu Yang, Ahmet T. Erdogan, Tughrul Arslan, Nick Barton
    System-Level Modeling and Multi-objective Evolutionary Design of Pipelined FFT Processors for Wireless OFDM Receivers. [Citation Graph (0, 0)][DBLP]
    ICES, 2007, pp:210-221 [Conf]
  83. Sajid Baloch, Tughrul Arslan, Adrian Stoica
    Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  84. Nazish Aslam, Mark Milward, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan
    Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-7 [Conf]
  85. Prakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan
    Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1875-1878 [Conf]
  86. Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan
    Low power variable block size motion estimation using pixel truncation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3663-3666 [Conf]
  87. L. Wang, Nizamettin Aydin, A. Astaras, M. Ahmadian, P. A. Hammond, T. B. Tang, Erik A. Johannessen, Tughrul Arslan, S. P. Beaumont, B. W. Flynn, A. F. Murray, Jonathan M. Cooper, David R. S. Cumming
    A sensor system on chip for wireless microsystems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  88. Indrajit Ahmed, Tughrul Arslan
    A low energy VLSI design of random block interleaver for 3GPP turbo decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  89. Evangelos F. Stefatos, I. Bravos, Tughrul Arslan
    Low-power implementation of FIR filters within an adaptive reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  90. Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
    An embedded low power reconfigurable fabric for finite state machine operations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  91. Mark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan, John S. Thompson
    A novel equaliser architecture with dynamic length optimisation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  92. Syamsiah Mashohor, Jonathan R. Evans, Tughrul Arslan
    Elitist selection schemes for genetic algorithm based printed circuit board inspection system. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:974-978 [Conf]
  93. Robert Thomson, Tughrul Arslan
    Techniques for the evolution of pipelined linear transforms. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:2476-2482 [Conf]
  94. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
    Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1281-1286 [Journal]

  95. VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond. [Citation Graph (, )][DBLP]


  96. A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications. [Citation Graph (, )][DBLP]


  97. Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture. [Citation Graph (, )][DBLP]


  98. Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications. [Citation Graph (, )][DBLP]


  99. An ILP formulation for task mapping and scheduling on multi-core architectures. [Citation Graph (, )][DBLP]


  100. Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture. [Citation Graph (, )][DBLP]


  101. Analog to Digital Converter Specification for UMTS/FDD Receiver Applications. [Citation Graph (, )][DBLP]


  102. SystemC-based Custom Reconfigurable Cores for Wireless Applications. [Citation Graph (, )][DBLP]


  103. Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems. [Citation Graph (, )][DBLP]


  104. Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures. [Citation Graph (, )][DBLP]


  105. The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures. [Citation Graph (, )][DBLP]


  106. System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems. [Citation Graph (, )][DBLP]


  107. H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture. [Citation Graph (, )][DBLP]


  108. A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays. [Citation Graph (, )][DBLP]


  109. Scalability of a Novel Shifting Balance Theory-Based Optimization Algorithm: A Comparative Study on a Cluster-Based Wireless Sensor Network. [Citation Graph (, )][DBLP]


  110. Nyquist-rate analog-to-digital converter specification for Zero-IF UMTS receiver. [Citation Graph (, )][DBLP]


  111. Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications. [Citation Graph (, )][DBLP]


  112. Efficient High-Level Power Estimation for Multi-standard Wireless Systems. [Citation Graph (, )][DBLP]


  113. Optimization of Reconfigurable Multi-core SOCs for Multi-standard Applications. [Citation Graph (, )][DBLP]


  114. Low Power Hardware Architecture for VBSME Using Pixel Truncation. [Citation Graph (, )][DBLP]


  115. A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays. [Citation Graph (, )][DBLP]


  116. System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design. [Citation Graph (, )][DBLP]


  117. A Power-Aware Algorithm for the Design of Reconfigurable Hardware during High Level Placement. [Citation Graph (, )][DBLP]


  118. A Novel Sampling Scheme for Efficient Analog to Digital Conversion. [Citation Graph (, )][DBLP]


  119. Multiobjective Optimal Design of MEMS-Based Reconfigurable and Evolvable Sensor Networks for Space Applications. [Citation Graph (, )][DBLP]


  120. Multi-Frequency Antenna design for Space-based Reconfigurable Satellite Sensor Node. [Citation Graph (, )][DBLP]


  121. A Multi-object GA Based Physical Placement Algorithm for Heterogeneous Dynamicaly Reconfigurable Arrays. [Citation Graph (, )][DBLP]


  122. Hybrid Communication Medium for Adaptive SoC Architectures. [Citation Graph (, )][DBLP]


  123. High Performance Embedded Reconfigurable Concatenated Convolution- Puncturing Fabric for 802.16. [Citation Graph (, )][DBLP]


  124. H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture. [Citation Graph (, )][DBLP]


  125. A genetic algorithm for energy efficient device scheduling in real-time systems. [Citation Graph (, )][DBLP]


  126. On the impact of modelling, robustness and diversity to the performance of a multi-objective evolutionary algorithm for digital VLSI system design. [Citation Graph (, )][DBLP]


  127. A multi-objective algorithm for the design of high performance reconfigurable architectures with embedded decoding. [Citation Graph (, )][DBLP]


  128. Fault tolerant cellular Genetic Algorithm. [Citation Graph (, )][DBLP]


  129. A novel shifting balance theory-based approach to optimization of an energy-constrained modulation scheme for wireless sensor networks. [Citation Graph (, )][DBLP]


  130. Evolutionary techniques for precise and real-time implementation of low-power FIR filters. [Citation Graph (, )][DBLP]


  131. A distributed cellular GA based architecture for real time GPS attitude determination. [Citation Graph (, )][DBLP]


  132. Analysis and Optimization of a Wireless Communication System for an Ingestable Sensor Microsystem. [Citation Graph (, )][DBLP]


  133. Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]


  134. Extensible software emulator for reconfigurable instruction cell based processors. [Citation Graph (, )][DBLP]


  135. Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer. [Citation Graph (, )][DBLP]


  136. MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors. [Citation Graph (, )][DBLP]


  137. A novel CMOS exponential approximation circuit. [Citation Graph (, )][DBLP]


  138. OFDM symbol timing synchronization system on a Reconfigurable Instruction Cell Array. [Citation Graph (, )][DBLP]


  139. Evaluation of contrast limited adaptive histogram equalization (CLAHE) enhancement on a FPGA. [Citation Graph (, )][DBLP]


  140. Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer. [Citation Graph (, )][DBLP]


  141. Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication. [Citation Graph (, )][DBLP]


  142. Low Computation and Memory Access for Variable Block Size Motion Estimation Using Pixel Truncation. [Citation Graph (, )][DBLP]


  143. I2S3 the Integrated Intelligent Secure Sensor Systems Project. [Citation Graph (, )][DBLP]


  144. Multi-Objective Evolutionary Optimizations of a Space-Based Reconfigurable Sensor Network under Hard Constraints. [Citation Graph (, )][DBLP]


  145. An Improved Particle Swarm Optimization Algorithm for Power-Efficient Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  146. The Re-emission Side Channel. [Citation Graph (, )][DBLP]


  147. Detecting Voltage Glitch Attacks on Secure Devices. [Citation Graph (, )][DBLP]


  148. Characterization of a Voltage Glitch Attack Detector for Secure Devices. [Citation Graph (, )][DBLP]


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