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Yinhe Han: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
    Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:53-58 [Conf]
  2. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Rapid and Energy-Efficient Testing for Embedded Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:8-13 [Conf]
  3. Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra
    Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:372-377 [Conf]
  4. Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:440-445 [Conf]
  5. Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li
    Pair Balance-Based Test Scheduling for SOCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:236-241 [Conf]
  6. Yinhe Han, Xiaowei Li
    Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:374-381 [Conf]
  7. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:298-305 [Conf]
  8. Ji Li, Yinhe Han, Xiaowei Li
    Deterministic and low power BIST based on scan slice overlapping. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5670-5673 [Conf]
  9. Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen
    Validation analysis and test flow optimization of VLSI chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5666-5669 [Conf]
  10. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
    Using MUXs Network to Hide Bunches of Scan Chains. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:238-243 [Conf]
  11. Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
    Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:201-209 [Journal]
  12. Jie Don, Yu Hu, Yinhe Han, Xiaowei Li
    An on-chip combinational decompressor for reducing test data volume. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  13. Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han
    Fast Packet Classification using Group Bit Vector. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  14. Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang
    Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2007, v:22, n:5, pp:673-680 [Journal]
  15. Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra
    Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:531-540 [Journal]

  16. M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. [Citation Graph (, )][DBLP]


  17. A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. [Citation Graph (, )][DBLP]


  18. Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. [Citation Graph (, )][DBLP]


  19. Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. [Citation Graph (, )][DBLP]


  20. A unified online Fault Detection scheme via checking of Stability Violation. [Citation Graph (, )][DBLP]


  21. Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. [Citation Graph (, )][DBLP]


  22. Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. [Citation Graph (, )][DBLP]


  23. Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. [Citation Graph (, )][DBLP]


  24. MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. [Citation Graph (, )][DBLP]


  25. Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy. [Citation Graph (, )][DBLP]


  26. A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. [Citation Graph (, )][DBLP]


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