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Publications of Author

1. Masanori Hashimoto, Hidetoshi Onodera
   Post-layout transistor sizing for power reduction in cell-based design. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:359-365 [Conf]
   
2. Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
   Timing analysis considering temporal supply voltage fluctuation. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:1098-1101 [Conf]
   
3. Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera
   A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:545-546 [Conf]
   
4. Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
   Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:723-728 [Conf]
   
5. Takashi Sato, Junji Ichimiya, Nobuto Ono, Kotaro Hachiya, Masanori Hashimoto
   On-chip thermal gradient analysis and temperature flattening for SoC design. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:1074-1077 [Conf]
   
6. Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera
   Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:9-10 [Conf]
   
7. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
   Representative frequency for interconnect R(f)L(f)C extraction. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:691-696 [Conf]
   
8. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
   Return path selection for loop RL extraction. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:1078-1081 [Conf]
   
9. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
   Interconnect RL extraction at a single representative frequency. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:515-520 [Conf]
   
10. Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
    A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:446-451 [Conf]
    
11. Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa
    Interconnect capacitance extraction for system LCD circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:160-163 [Conf]
    
12. Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
    Equivalent Waveform Propagation for Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:169-175 [Conf]
    
13. Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera
    Timing analysis considering spatial power/ground level variation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:814-820 [Conf]
    
14. Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye
    A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:47-53 [Conf]
    
15. Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera
    Crosstalk Noise Estimation for Generic RC Trees. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:110-117 [Conf]
    
16. Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
    A power optimization method considering glitch reduction by gate sizing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:221-226 [Conf]
    
17. Masanori Hashimoto, Hidetoshi Onodera
    A performance optimization method by gate sizing using statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:111-116 [Conf]
    
18. Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera
    Crosstalk noise optimization by post-layout transistor sizing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:126-130 [Conf]
    
19. Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
    Capturing crosstalk-induced waveform for accurate static timing analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:18-23 [Conf]
    
20. Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
    Effects of on-chip inductance on power distribution grid. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:63-69 [Conf]
    
21. Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera
    Automatic Generation of Standard Cell Library in VDSM Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:36-41 [Conf]
    
22. Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera
    Statistical Analysis of Clock Skew Variation in H-Tree Structure. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:402-407 [Conf]
    
23. Kenichi Shinkai, Masanori Hashimoto, Takao Onoye
    Future Prediction of Self-Heating in Short Intra-Block Wires. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:660-665 [Conf]
    
24. Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera
    Experimental Study on Cell-Base High-Performance Datapath Design. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:283-287 [Conf]
    
25. Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
    Equivalent waveform propagation for static timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:498-508 [Journal]
    
26. 
    Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. [Citation Graph (, )][DBLP]
    
    
27. 
    High performance current-mode differential logic. [Citation Graph (, )][DBLP]
    
    
28. 
    Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. [Citation Graph (, )][DBLP]
    
    
29. 
    High performance on-chip differential signaling using passive compensation for global communication. [Citation Graph (, )][DBLP]
    
    
30. 
    Coarse-grained dynamically reconfigurable architecture with flexible reliability. [Citation Graph (, )][DBLP]
    
    
31. 
    Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. [Citation Graph (, )][DBLP]
    
    
32. 
    Clock skew reduction by self-compensating manufacturing variability with on-chip sensors. [Citation Graph (, )][DBLP]
    
    
33. 
    Decoupling capacitance allocation for timing with statistical noise model and timing analysis. [Citation Graph (, )][DBLP]
    
    
34. 
    Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. [Citation Graph (, )][DBLP]
    
    
35. 
    On-chip high performance signaling using passive compensation. [Citation Graph (, )][DBLP]
    
    
36. 
    Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. [Citation Graph (, )][DBLP]
    
    
37. 
    Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. [Citation Graph (, )][DBLP]
    
    
38. 
    Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. [Citation Graph (, )][DBLP]
    
    
39. 
    Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. [Citation Graph (, )][DBLP]
    
    
40. 
    A case for exploiting complex arithmetic circuits towards performance yield enhancement. [Citation Graph (, )][DBLP]
    
    
41. 
    Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. [Citation Graph (, )][DBLP]
    
    
42. 
    Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. [Citation Graph (, )][DBLP]