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Keishi Sakanushi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. M. AbdElSalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Enabling RTOS simulation modeling in a system level design language. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:936-939 [Conf]
  2. Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Synthesizable HDL generation method for configurable VLIW processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:842-845 [Conf]
  3. Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa
    Pack instruction generation for media pUsing multi-valued decision diagram. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:154-159 [Conf]
  4. M. AbdElSalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:554-559 [Conf]
  5. Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Architecture-Level Performance Estimation for IP-Based Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1002-1007 [Conf]
  6. Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin
    An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:61-68 [Conf]
  7. Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita
    The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:418-425 [Conf]
  8. Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani
    The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:267-274 [Conf]
  9. H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2004, pp:824-830 [Conf]
  10. Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai
    S-sequence: a new floorplan representation method preserving room abutment relationships. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:505-508 [Conf]
  11. Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai
    A Code Selection Method for SIMD Processors with PACK Instructions. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:66-80 [Conf]
  12. Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:290-295 [Conf]
  13. M. AbdElSalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  14. A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. [Citation Graph (, )][DBLP]


  15. Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. [Citation Graph (, )][DBLP]


  16. A low power VLIW processor generation method by means of extracting non-redundant activation conditions. [Citation Graph (, )][DBLP]


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