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Publications of Author

1. Kazumi Hatayama, Rochit Rajsuman
   Opportunities with the open architecture test system. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:334- [Conf]
   
2. Hiroshi Date, Michinobu Nakao, Kazumi Hatayama
   A parallel sequential test generation system DESCARTES based on real-valued logic simulation. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1995, pp:252-258 [Conf]
   
3. Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto
   Application of a Design for Delay Testability Approach to High Speed Logic LSIs. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1997, pp:112-115 [Conf]
   
4. Kazumi Hatayama, Michinobu Nakao, Yasuo Sato
   At-Speed Built-in Test for Logic Circuits with Multiple Clocks. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2002, pp:292-297 [Conf]
   
5. Michinobu Nakao, Kazumi Hatayama, Isao Higashi
   Accelerated Test Points Selection Method for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1997, pp:359-0 [Conf]
   
6. Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo
   Test Generation for Multiple-Threshold Gate-Delay Fault Model. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2001, pp:244-0 [Conf]
   
7. Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi
   Sequential Test Generation Based on Real-Value Logic. [Citation Graph (0, 0)][DBLP]
   ITC, 1992, pp:41-48 [Conf]
   
8. Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama
   Enhanced Delay Test Generator for High-Speed Logic LSIs. [Citation Graph (0, 0)][DBLP]
   ITC, 1989, pp:161-165 [Conf]
   
9. Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
   Application of High-Quality Built-In Test to Industrial Designs. [Citation Graph (0, 0)][DBLP]
   ITC, 2002, pp:1003-1012 [Conf]
   
10. Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada
    Low overhead test point insertion for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:348-357 [Conf]
    
11. Kazumi Hatayama
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:200-201 [Conf]
    
12. Kazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada
    A practical approach to instruction-based test generation for functional modules of VLSI processors. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:17-23 [Conf]
    
13. 
    An Adaptive Test for Parametric Faults Based on Statistical Timing Information. [Citation Graph (, )][DBLP]
    
    
14. 
    Estimation of delay test quality and its application to test generation. [Citation Graph (, )][DBLP]
    
    
15. 
    Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. [Citation Graph (, )][DBLP]
    
    
16. 
    A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. [Citation Graph (, )][DBLP]