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Publications of Author

1. Kazumi Hatayama, Rochit Rajsuman
   Opportunities with the open architecture test system. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:334- [Conf]
   
2. Rochit Rajsuman
   New opportunities with the open architecture test system. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:335- [Conf]
   
3. Rochit Rajsuman
   Extending EDA Environment From Design to Test. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2002, pp:386-391 [Conf]
   
4. Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya
   CMOS Stuck-open Fault Detection Using Single Test Patterns. [Citation Graph (0, 0)][DBLP]
   DAC, 1989, pp:714-717 [Conf]
   
5. Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana
   On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates. [Citation Graph (0, 0)][DBLP]
   DAC, 1987, pp:244-250 [Conf]
   
6. Rochit Rajsuman
   An Overview of the Open Architecture Test System. [Citation Graph (0, 0)][DBLP]
   DELTA, 2004, pp:341-348 [Conf]
   
7. Rochit Rajsuman
   Innovation In Test: Where Are We. [Citation Graph (0, 0)][DBLP]
   DELTA, 2006, pp:289-294 [Conf]
   
8. Rochit Rajsuman
   Towards The Methodology of On-line Diagnosis. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2006, pp:76- [Conf]
   
9. Jerry Katz, Rochit Rajsuman
   A new paradigm in test for the next millennium. [Citation Graph (0, 0)][DBLP]
   ITC, 2000, pp:468-476 [Conf]
   
10. Roderick McConnell, Rochit Rajsuman, Eric A. Nelson, Jeffrey Dreibelbis
    Test and repair of large embedded DRAMs. I. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:163-172 [Conf]
    
11. Rochit Rajsuman
    Testing The Tester. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:27- [Conf]
    
12. Rochit Rajsuman
    Testing The Tester. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:30- [Conf]
    
13. Rochit Rajsuman
    Can IC Test Learn from How a Tester is Tested. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1186- [Conf]
    
14. Rochit Rajsuman
    Challenge of the 90's: Testing CoreWare^TM Based ASICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:940- [Conf]
    
15. Rochit Rajsuman
    Testing a system-on-a-chip with embedded microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:499-508 [Conf]
    
16. Rochit Rajsuman, Masuda Noriyuki
    Open Architecture Test System: System Architecture and Design. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:403-412 [Conf]
    
17. S. Hwang, Rochit Rajsuman, Yashwant K. Malaiya
    On the testing of microprogrammed processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1990, pp:260-266 [Conf]
    
18. S. Hwang, Rochit Rajsuman, Scott Davidson
    I_DDQ Detection of CMOS Bridging Faults by Stuck-At Fault Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:183-186 [Conf]
    
19. Rochit Rajsuman, D. A. Penry
    Coverage of Bridging Faults by Random Testing in I_DDQ Test Environment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:136-139 [Conf]
    
20. Rochit Rajsuman
    Design and Test of Large Embedded Memories: An Overview. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:3, pp:16-27 [Journal]
    
21. Rochit Rajsuman, Francky Catthoor
    Guest Editors' Intoduction: The New World of Large Embedded Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:3, pp:3-4 [Journal]
    
22. Rochit Rajsuman
    A new testing method for EEPLA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:935-939 [Journal]
    
23. Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana
    Limitations of switch level analysis for bridging faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:807-811 [Journal]