|
Search the dblp DataBase
Terumine Hayashi:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase
Test data compression technique using selective don't-care identification. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:230-233 [Conf]
- Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. [Citation Graph (0, 0)][DBLP] ASP-DAC, 1999, pp:291-294 [Conf]
- Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi
On a Logical Fault Model H1SGLF for Enhancing Defect Coverage. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1998, pp:102-107 [Conf]
- Tsuyoshi Shinogi, Terumine Hayashi
A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1999, pp:164-0 [Conf]
- Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki
Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1997, pp:16-21 [Conf]
- Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi
Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2001, pp:76-81 [Conf]
- Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi
Cyclic greedy generation method for limited number of IDDQ tests. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2000, pp:362-0 [Conf]
- Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa
A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2005, pp:366-371 [Conf]
- Tsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka
Between-Core Vector Overlapping for Test Cost Reduction in Core Testing. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2003, pp:268-273 [Conf]
- Kuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi
A delay test system for high speed logic LSI's. [Citation Graph (0, 0)][DBLP] DAC, 1986, pp:786-790 [Conf]
- Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani
Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. [Citation Graph (0, 0)][DBLP] ICCAD, 1991, pp:332-335 [Conf]
- Haruhiko Takase, Tsuyoshi Shinogi, Terumine Hayashi, Hidehiko Kita
Evaluation Function for Fault Tolerant Multi-Layer Neural Networks. [Citation Graph (0, 0)][DBLP] IJCNN (3), 2000, pp:521-526 [Conf]
- Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi
Sequential Test Generation Based on Real-Value Logic. [Citation Graph (0, 0)][DBLP] ITC, 1992, pp:41-48 [Conf]
- Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama
Enhanced Delay Test Generator for High-Speed Logic LSIs. [Citation Graph (0, 0)][DBLP] ITC, 1989, pp:161-165 [Conf]
- Tsuyoshi Shinogi, Terumine Hayashi
A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault. [Citation Graph (0, 0)][DBLP] VTS, 1998, pp:112-117 [Conf]
- Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase
On Test Data Compression Using Selective Don't-Care Identification. [Citation Graph (0, 0)][DBLP] J. Comput. Sci. Technol., 2005, v:20, n:2, pp:210-215 [Journal]
- Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
An enhanced fault model for high defect coverage. [Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 2001, v:32, n:6, pp:36-44 [Journal]
- Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki
Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits. [Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 1999, v:30, n:7, pp:55-68 [Journal]
Descriptive Answer Clustering System for Immediate Feedback. [Citation Graph (, )][DBLP]
Enhancing both generalization and fault tolerance of multilayer neural networks. [Citation Graph (, )][DBLP]
Shape of error surfaces in SpikeProp. [Citation Graph (, )][DBLP]
Search in 0.002secs, Finished in 0.303secs
|