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Jochen A. G. Jess: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess
    High-level synthesis scheduling and allocation using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
    Statistical timing for parametric yield prediction of digital integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:932-937 [Conf]
  3. Luiz C. V. dos Santos, Jochen A. G. Jess
    A Reordering Technique for Efficient Code Motion. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:296-299 [Conf]
  4. Adwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess
    Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:593-598 [Conf]
  5. Hua Xue, Ed P. Huijbregts, Jochen A. G. Jess
    Routing for Manufacturability. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:402-406 [Conf]
  6. Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
    Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:125-131 [Conf]
  7. Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
    A Constraint Driven Approach to Loop Pipelining and Register Binding. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:377-383 [Conf]
  8. Carlos A. Alba Pinto, Bart Mesman, Koen van Eijk, Jochen A. G. Jess
    Constraint satisfaction for storage files with Fifos or stacks during scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:824- [Conf]
  9. Luiz C. V. dos Santos, Jochen A. G. Jess
    Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:609-0 [Conf]
  10. Hua Xue, Chennian Di, Jochen A. G. Jess
    Fast Multi-Layer Critical Area Computation. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:117-124 [Conf]
  11. Hua Xue, Chennian Di, Jochen A. G. Jess
    Probability Analysis for CMOS Floating Gate Faults. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:443-448 [Conf]
  12. Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess
    On Design Rule Correct Maze Routing. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:407-411 [Conf]
  13. Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess
    Constraint Satisfaction for Relative Location Assignment and Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:384-390 [Conf]
  14. Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
    Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:474-480 [Conf]
  15. Adwin H. Timmer, Jochen A. G. Jess
    Execution interval analysis under resource constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:454-459 [Conf]
  16. Hua Xue, Chennian Di, Jochen A. G. Jess
    A net-oriented method for realistic fault analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:78-83 [Conf]
  17. Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
    PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:164-169 [Conf]
  18. M. J. M. Heijiligers, H. A. Hilderink, Adwin H. Timmer, Jochen A. G. Jess
    NEAT: An Object Oriented High-Level Synthesis Interface. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:233-236 [Conf]
  19. Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
    Constraint Analysis for DSP Code Generation. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:33-40 [Conf]
  20. Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen
    Phase coupled operation assignment for VLIW processors with distributed register files. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:118-123 [Conf]
  21. Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess
    Static resource models of instruction sets. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:159-164 [Conf]
  22. Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess
    A Constructive Method for Exploiting Code Motion. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:51-56 [Conf]
  23. Chennian Di, Jochen A. G. Jess
    On Accurate Modeling and Efficient Simulation of CMOS Opens. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:875-882 [Conf]
  24. Eric Bruls, F. Camerik, H. J. Kretschman, Jochen A. G. Jess
    A Generic Method to Develop a Defect Monitoring System for IC Processes. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:218-227 [Conf]
  25. F. Camerik, P. A. J. Dirks, Jochen A. G. Jess
    Qualification and Quantification of Process-Induced Product-Related Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:643-652 [Conf]
  26. M. M. A. van Rosmalen, Keith Baker, Eric Bruls, Jochen A. G. Jess
    Parameter Monitoring: Advantages and Pitfalls. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:115-124 [Conf]
  27. Ed P. Huijbregts, Jochen A. G. Jess
    A Multiple Terminal Net Routing Algorithm Using Failure Prediction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:84-89 [Conf]
  28. Jochen A. G. Jess
    Codeübersetzung unter Zeitvorgaben für eingebettete Signalprozessoren. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2003, v:45, n:6, pp:- [Journal]
  29. Jochen A. G. Jess, H. G. M. Kees
    A Data Structure for Parallel L/U Decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:3, pp:231-239 [Journal]
  30. Chennian Di, Jochen A. G. Jess
    An efficient CMOS bridging fault simulator: with SPICE accuracy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1071-1080 [Journal]
  31. Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
    Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1424-1434 [Journal]
  32. José Pineda de Gyvez, Jochen A. G. Jess
    On the design and implementation of a wafer yield editor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:920-925 [Journal]
  33. Jochen A. G. Jess
    Designing electronic engines with electronic engines: 40 years ofbootstrapping of a technology upon itself. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1404-1427 [Journal]
  34. Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
    Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2376-2392 [Journal]
  35. Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
    Constraint analysis for DSP code generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:44-57 [Journal]
  36. Koen van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess
    Constraint analysis for code generation: basic techniques and applications in FACTS. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:4, pp:774-793 [Journal]
  37. Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess
    A code-motion pruning technique for global scheduling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:1-38 [Journal]
  38. Ed P. Huijbregts, Jochen A. G. Jess
    General gate array routing using a k-terminal net routing algorithm with failure prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:473-481 [Journal]

  39. PROPHID: a data-driven multi-processor architecture for high-performance DSP. [Citation Graph (, )][DBLP]


  40. Gate sizing in MOS digital circuits with linear programming. [Citation Graph (, )][DBLP]


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