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Author:
Kewal K. Saluja: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
    Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:659-664 [Conf]
  2. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
    Fault models and test generation for IDDQ testing: embedded tutorial. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:509-514 [Conf]
  3. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    Multiple Faults: Modeling, Simulation and Test. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:592-597 [Conf]
  4. Fei Li, Lei He, Kewal K. Saluja
    Estimation of Maximum Power-up Current. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:51-58 [Conf]
  5. Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
    Minimizing Energy Consumption for High-Performance Processing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:199-206 [Conf]
  6. Dong Hyun Baik, Kewal K. Saluja
    State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:272-277 [Conf]
  7. Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja
    A Class of Linear Space Compactors for Enhanced Diagnostic. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:260-265 [Conf]
  8. Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
    Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:312-317 [Conf]
  9. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
    Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:141-146 [Conf]
  10. Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu
    Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:242-247 [Conf]
  11. Mohammad Gh. Mohammad, Kewal K. Saluja
    Stress Test for Disturb Faults in Non-Volatile Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:384-389 [Conf]
  12. Kewal K. Saluja
    Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:2- [Conf]
  13. Marong Phadoongsidhi, Kim T. Le, Kewal K. Saluja
    A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:182-0 [Conf]
  14. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Software-Based Delay Fault Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:68-71 [Conf]
  15. Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu
    Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:63-0 [Conf]
  16. Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
    Design for Diagnosability of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:144-149 [Conf]
  17. Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
    Fault Diagnosis for Physical Defects of Unknown Behaviors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:236-241 [Conf]
  18. Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya
    BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:385-391 [Conf]
  19. Faisal Rashid, Kewal K. Saluja, Parameswaran Ramanathan
    Fault Tolerance through Re-Execution in Multiscalar Architecture. [Citation Graph (0, 0)][DBLP]
    DSN, 2000, pp:482-491 [Conf]
  20. Kewal K. Saluja, Sudhakar M. Reddy
    Multiple Faults in Reed-Muller Canonic Networks [Citation Graph (0, 0)][DBLP]
    FOCS, 1972, pp:185-191 [Conf]
  21. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Testing Superscalar Processors in Functional Mode. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:747-750 [Conf]
  22. Manoj Franklin, Kewal K. Saluja
    Pattern Sensitive Fault Testing of RAMs with Bullt-in ECC. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:385-392 [Conf]
  23. Ning Jiang, Richard M. Chou, Kewal K. Saluja
    Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:41-49 [Conf]
  24. Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja
    Behavioral Synthesis of Testable Designs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:436-445 [Conf]
  25. Ashutosh Mujumdar, Kewal K. Saluja, Rajiv Jain
    Incorporating Testability Considerations in High-Level Systhesis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:272-279 [Conf]
  26. Lama Nachman, Kewal K. Saluja, Shambhu J. Upadhyaya, Robert Reuse
    Random Pattern Testing for Sequential Circuits Revisited. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:44-52 [Conf]
  27. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:300-0 [Conf]
  28. Hao Zheng, Kewal K. Saluja, Rajiv Jain
    Test application time reduction for scan based sequential circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:188-191 [Conf]
  29. Soo Young Lee, Kewal K. Saluja
    An algorithm to reduce test application time in full scan designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:17-20 [Conf]
  30. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    A yield improvement methodology using pre- and post-silicon statistical clock scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:611-618 [Conf]
  31. Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
    On per-test fault diagnosis using the X-fault model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:633-640 [Conf]
  32. Xiaoqing Wen, Kewal K. Saluja
    A new method towards achieving global optimality in technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:9-12 [Conf]
  33. Marong Phadoongsidhi, Kewal K. Saluja
    Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:42-47 [Conf]
  34. Eric F. Weglarz, Kewal K. Saluja, T. M. Mak
    Testing of Hard Faults in Simultaneous Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:95-100 [Conf]
  35. Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja
    Analytic modeling of detection latency in mobile sensor networks. [Citation Graph (0, 0)][DBLP]
    IPSN, 2006, pp:194-201 [Conf]
  36. Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
    Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:224-231 [Conf]
  37. Soo Young Lee, Kewal K. Saluja
    Efficient Test Vectors for ISCAS Sequential Benchmark Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1511-1514 [Conf]
  38. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-based delay fault self-testing of pipelined processor cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5686-5689 [Conf]
  39. Xiangning Yang, Kewal K. Saluja
    Combating NBTI Degradation via Gate Sizing. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:47-52 [Conf]
  40. Kim T. Le, Kewal K. Saluja
    A Novel Approach for Testing Memories Using a Built-In Self Testing Technique. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:830-839 [Conf]
  41. Manoj Franklin, Kewal K. Saluja
    An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:675-684 [Conf]
  42. Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
    Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:327-336 [Conf]
  43. Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita
    A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:574-582 [Conf]
  44. Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu
    On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:568-577 [Conf]
  45. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Combinational test generation for various classes of acyclic sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1078-1087 [Conf]
  46. Matthew L. King, Kewal K. Saluja
    Testing Micropipelined Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:329-338 [Conf]
  47. Kozo Kinoshita, Kewal K. Saluja
    Built-in Testing of Memory Using On-chip Compact Testing Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:271-281 [Conf]
  48. Kewal K. Saluja, Mark G. Karpovsky
    Testing Computer Hardware through Data Compression in Space and Time. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:83-88 [Conf]
  49. Kewal K. Saluja, Li Shen, Stephen Y. H. Su
    A Simplified Algorithm for Testing Microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:668-675 [Conf]
  50. Thomas Clouqueur, Veradej Phipatanasuphorn, Parameswaran Ramanathan, Kewal K. Saluja
    Sensor deployment strategy for target detection. [Citation Graph (0, 0)][DBLP]
    WSNA, 2002, pp:42-48 [Conf]
  51. Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu
    An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:275-282 [Conf]
  52. Dong Hyun Baik, Kewal K. Saluja
    Test Cost Reduction Using Partitioned Grid Random Access Scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:169-174 [Conf]
  53. Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara
    Random Access Scan: A solution to test power, test data volume and test time. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:883-888 [Conf]
  54. Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja
    Exclusive Test and its Applications to Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:143-148 [Conf]
  55. Richard M. Chou, Kewal K. Saluja
    Sequential Circuit Testing: From DFT to SFT. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:274-278 [Conf]
  56. Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
    Power Constraint Scheduling of Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:271-274 [Conf]
  57. Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, Hiroshi Takahashi
    Efficient Signature-Based Fault Diagnosis Using Variable Size Windows. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:391-396 [Conf]
  58. Manoj Franklin, Kewal K. Saluja
    An Algorithm to Test Reconfigured RAMs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:359-364 [Conf]
  59. Manoj Franklin, Kewal K. Saluja, Kyuchull Kim
    Fast computation of MISR signatures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:414-418 [Conf]
  60. Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
    Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:72-77 [Conf]
  61. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Multiple Faults: Modeling, Simulation and Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:592-597 [Conf]
  62. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:143-148 [Conf]
  63. Seiji Kajihara, Kewal K. Saluja
    On Test Pattern Compaction Using Random Pattern Fault Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:464-469 [Conf]
  64. Timothy John Lambert, Kewal K. Saluja
    Methods for Dynamic Test Vector compaction in Sequential Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:166-169 [Conf]
  65. Fei Li, Lei He, Kewal K. Saluja
    Estimation of Maximum Power-Up Current. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:51-0 [Conf]
  66. Mohammad Gh. Mohammad, Kewal K. Saluja
    Electrical Model For Program Disturb Faults in Non-Volatile Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:217-222 [Conf]
  67. Mohammad Gh. Mohammad, Kewal K. Saluja, Alex Yap
    Testing Flash Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:406-411 [Conf]
  68. Marong Phadoongsidhi, Kewal K. Saluja
    Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:437-442 [Conf]
  69. Marong Phadoongsidhi, Kewal K. Saluja
    SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:820-823 [Conf]
  70. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-Based Delay Fault Self-Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:933-0 [Conf]
  71. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    False Path and Clock Scheduling Based Yield-Aware Gate Sizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:423-426 [Conf]
  72. Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara
    Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:300-305 [Conf]
  73. Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
    Minimizing Energy Consumption for High-Performance Processing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:199-0 [Conf]
  74. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu
    Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:781-786 [Conf]
  75. Xiangning Yang, Eric F. Weglarz, Kewal K. Saluja
    On NBTI Degradation Process in Digital Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:723-730 [Conf]
  76. Kim T. Le, Dong Hyun Baik, Kewal K. Saluja
    Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:769-774 [Conf]
  77. Richard M. Chou, Kewal K. Saluja
    Testable Sequential Circuit Design: A Partition and Resynthesis Approach. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:62-67 [Conf]
  78. Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja
    An optimized testable architecture for finite state machines. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:164-169 [Conf]
  79. Mohammad Gh. Mohammad, Kewal K. Saluja
    Flash Memory Disturbances: Modeling and Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:218-224 [Conf]
  80. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
    A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:58-65 [Conf]
  81. Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
    On Low-Capture-Power Test Generation for Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:265-270 [Conf]
  82. Manoj Franklin, Kewal K. Saluja
    Built-in Self-testing of Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:10, pp:45-56 [Journal]
  83. C. Boswell, Kewal K. Saluja, Kozo Kinoshita
    Design of Programmable Logic Arrays for Parallel Testing. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 1985, v:1, n:1, pp:5-16 [Journal]
  84. Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja
    A Tutorial on Built-in Self-Test. I. Principles. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:1, pp:73-82 [Journal]
  85. Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja
    A Tutorial on Built-In Self-Test, Part 2: Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:2, pp:69-77 [Journal]
  86. Kewal K. Saluja, Kyuchull Kim
    Improved Test Generation for High-Activity Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:4, pp:26-31 [Journal]
  87. Kewal K. Saluja, Chin-Foo See
    An Efficient Signature Computation Method. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:4, pp:22-26 [Journal]
  88. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    Yield-Driven, False-Path-Aware Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:214-222 [Journal]
  89. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Delay Fault Testing of Processor Cores in Functional Mode. [Citation Graph (0, 0)][DBLP]
    IEICE Transactions, 2005, v:88, n:3, pp:610-618 [Journal]
  90. Yong Chang Kim, Kewal K. Saluja
    Sequential test generators: past, present and future. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:41-54 [Journal]
  91. Kewal K. Saluja, Brian D. O. Anderson
    Fault diagnosis in loop-connected systems. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1980, v:21, n:1, pp:75-92 [Journal]
  92. Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
    Fault Diagnosis of Physical Defects Using Unknown Behavior Model. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:187-194 [Journal]
  93. Thomas Clouqueur, Veradej Phipatanasuphorn, Parameswaran Ramanathan, Kewal K. Saluja
    Sensor Deployment Strategy for Detection of Targets Traversing a Region. [Citation Graph (0, 0)][DBLP]
    MONET, 2003, v:8, n:4, pp:453-461 [Journal]
  94. Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
    Static test compaction for IDDQ testing of bridging faults in sequential circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2000, v:31, n:11, pp:41-50 [Journal]
  95. Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
    Design and Analysis of a Gracefully Degrading Interleaved Memory System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:1, pp:63-71 [Journal]
  96. Thomas Clouqueur, Kewal K. Saluja, Parameswaran Ramanathan
    Fault Tolerance in Collaborative Sensor Networks for Target Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:3, pp:320-333 [Journal]
  97. Gary L. Craig, Charles R. Kime, Kewal K. Saluja
    Test Scheduling and Control for VLSI Built-In Self-Test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:9, pp:1099-1109 [Journal]
  98. Manoj Franklin, Kewal K. Saluja
    Hypergraph Coloring and Reconfigured RAM Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:6, pp:725-736 [Journal]
  99. Kozo Kinoshita, Kewal K. Saluja
    Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:10, pp:862-870 [Journal]
  100. Todd P. Kelsey, Kewal K. Saluja, Soo Young Lee
    An Efficient Algorithm for Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:11, pp:1361-1371 [Journal]
  101. Lama Nachman, Kewal K. Saluja, Shambhu J. Upadhyaya, Robert Reuse
    A Novel Approach to Random Pattern Testing of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:1, pp:129-134 [Journal]
  102. Sudhakar M. Reddy, Kewal K. Saluja, Mark G. Karpovsky
    A Data Compression Technique for Built-In Self-Test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:9, pp:1151-1156 [Journal]
  103. Kewal K. Saluja
    Synchronous Sequential Machines: A Modular and Testable Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:11, pp:1020-1025 [Journal]
  104. Kewal K. Saluja, Ramaswami Dandapani
    An Alternative to Scan Design Methods for Sequential Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:4, pp:384-388 [Journal]
  105. Kewal K. Saluja, Ramaswami Dandapani
    Testable Design of Single-Output Sequential Machines Using Checking Experiments. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:7, pp:658-662 [Journal]
  106. Kewal K. Saluja, Kozo Kinoshita
    Test Pattern Generation for API Faults in RAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:3, pp:284-287 [Journal]
  107. Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara
    An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:11, pp:1038-1046 [Journal]
  108. Kewal K. Saluja, E. H. Ong
    Minimization of Reed-Muller Canonic Expansion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:7, pp:535-537 [Journal]
  109. Kewal K. Saluja, Sudhakar M. Reddy
    Fault Detecting Test Sets for Reed-Muller Canonic Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:10, pp:995-998 [Journal]
  110. Keiho Akiyama, Kewal K. Saluja
    A method of reducing aliasing in a built-in self-test environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:548-553 [Journal]
  111. Manoj Franklin, Kewal K. Saluja
    Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1081-1087 [Journal]
  112. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Combinational automatic test pattern generation for acyclic sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:948-956 [Journal]
  113. Soo Young Lee, Kewal K. Saluja
    Test application time reduction for sequential circuits with scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1128-1140 [Journal]
  114. Chun-Yeh Liu, Kewal K. Saluja
    An efficient algorithm for bipartite PLA folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1839-1847 [Journal]
  115. Mohammad Gh. Mohammad, Kewal K. Saluja
    Optimizing program disturb fault tests using defect-based testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:905-915 [Journal]
  116. Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja
    Incorporating performance and testability constraints during binding in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1212-1225 [Journal]
  117. Kewal K. Saluja, Rajiv Sharma, Charles R. Kime
    A concurrent testing technique for digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1250-1260 [Journal]
  118. Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu
    On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:362-368 [Journal]
  119. Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu
    A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:252-263 [Journal]
  120. Shambhu J. Upadhyaya, Kewal K. Saluja
    A new approach to the design of built-in self-testing PLAs for high fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:60-67 [Journal]
  121. Shambhu J. Upadhyaya, Kewal K. Saluja
    A Wachtdog Processor Based General Rollback Technique with Multiple Retries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1986, v:12, n:1, pp:87-95 [Journal]
  122. Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
    Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:527-532 [Conf]
  123. Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja
    Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  124. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1203-1215 [Journal]
  125. Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
    Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:790-800 [Journal]
  126. Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
    Scheduling tests for VLSI systems under power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:175-185 [Journal]
  127. Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja
    Efficient Test Set Modification for Capture Power Reduction. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:319-330 [Journal]
  128. Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
    Energy Estimation of the Memory Subsystem in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:325-332 [Journal]

  129. Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies. [Citation Graph (, )][DBLP]


  130. Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. [Citation Graph (, )][DBLP]


  131. Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. [Citation Graph (, )][DBLP]


  132. An accurate flip-flop selection technique for reducing logic SER. [Citation Graph (, )][DBLP]


  133. DX-compactor: distributed X-compaction for SoCs. [Citation Graph (, )][DBLP]


  134. Energy-efficient redundant execution for chip multiprocessors. [Citation Graph (, )][DBLP]


  135. Moments Based Blind Calibration in Mobile Sensor Networks. [Citation Graph (, )][DBLP]


  136. Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. [Citation Graph (, )][DBLP]


  137. Implementing high availability memory with a duplication cache. [Citation Graph (, )][DBLP]


  138. Testing Flash Memories for Tunnel Oxide Defects. [Citation Graph (, )][DBLP]


  139. NBTI Degradation: A Problem or a Scare? [Citation Graph (, )][DBLP]


  140. WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. [Citation Graph (, )][DBLP]


  141. On Minimization of Test Application Time for RAS. [Citation Graph (, )][DBLP]


  142. Modified T-Flip-Flop based scan cell for RAS. [Citation Graph (, )][DBLP]


  143. Calibrating Nonlinear Mobile Sensors. [Citation Graph (, )][DBLP]


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