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Title:
Author:
Kozo Kinoshita: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
    Fault models and test generation for IDDQ testing: embedded tutorial. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:509-514 [Conf]
  2. Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita
    A high-speed IDDQ sensor implementation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:356-361 [Conf]
  3. Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita
    A High-Speed IDDQ Sensor for Low-Voltage ICs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:327-0 [Conf]
  4. Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
    A BIST Circuit for IDDQ Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:390-395 [Conf]
  5. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
    Test sequence compaction by reduced scan shift and retiming. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:169-175 [Conf]
  6. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
    Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:94-99 [Conf]
  7. Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
    Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:312-317 [Conf]
  8. Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita
    Test sequence compaction for sequential circuits with reset states. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:165-170 [Conf]
  9. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
    Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:141-146 [Conf]
  10. Hideyuki Ichihara, Kozo Kinoshita
    On Acceleration of Logic Circuits Optimization Using Implication Relations. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:222-227 [Conf]
  11. Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita
    An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:58-63 [Conf]
  12. Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
    On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:147-152 [Conf]
  13. Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita
    An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:22-0 [Conf]
  14. Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita
    Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:272-277 [Conf]
  15. Arabi Keshk, Kozo Kinoshita, Yukiya Miura
    Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:121-126 [Conf]
  16. Arabi Keshk, Kozo Kinoshita, Yukiya Miura
    IDDQ Current Dependency on Test Vectors and Bridging Resistance. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:158-163 [Conf]
  17. Arabi Keshk, Yukiya Miura, Kozo Kinoshita
    Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:120-124 [Conf]
  18. Toshiyuki Maeda, Kozo Kinoshita
    Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:350-355 [Conf]
  19. Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
    Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:469- [Conf]
  20. Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
    Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:176-181 [Conf]
  21. Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita
    IDDQ Sensing Technique for High Speed IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:111-116 [Conf]
  22. Hiroaki Ueda, Kozo Kinoshita
    Low power design and its testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:361-366 [Conf]
  23. Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
    Design for Diagnosability of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:144-149 [Conf]
  24. Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita
    Transistor leakage fault location with ZDDQ measurement. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:51-57 [Conf]
  25. Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
    Fault Diagnosis for Physical Defects of Unknown Behaviors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:236-241 [Conf]
  26. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
    Reducing Scan Shifts Using Folding Scan Trees. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:6-11 [Conf]
  27. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
    Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:102-106 [Conf]
  28. Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita
    Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:92-98 [Conf]
  29. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
    On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:269-274 [Conf]
  30. Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita
    A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:38-43 [Conf]
  31. Seiji Kajihara, Haruko Shiba, Kozo Kinoshita
    Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:263-270 [Conf]
  32. Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
    Synthesis for Testability by Sequential Redundancy Removal Using Retiming. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:33-40 [Conf]
  33. Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
    On Test Generation with A Limited Number of Tests. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:12-15 [Conf]
  34. Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita
    Test generation for multiple faults based on parallel vector pair analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:436-439 [Conf]
  35. Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
    On per-test fault diagnosis using the X-fault model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:633-640 [Conf]
  36. Yukiya Miura, Sachio Naito, Kozo Kinoshita
    A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:77-80 [Conf]
  37. Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
    Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:327-336 [Conf]
  38. Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita
    A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:574-582 [Conf]
  39. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
    Reduced Scan Shift: A New Testing Method for Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:624-630 [Conf]
  40. Noriyoshi Itazaki, Kozo Kinoshita
    Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:105-112 [Conf]
  41. Kozo Kinoshita, Kewal K. Saluja
    Built-in Testing of Memory Using On-chip Compact Testing Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:271-281 [Conf]
  42. Toshiyuki Maeda, Kozo Kinoshita
    Precise test generation for resistive bridging faults of CMOS combinational circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:510-519 [Conf]
  43. Yukiya Miura, Kozo Kinoshita
    Circuit Design for Built-in Current Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:873-881 [Conf]
  44. Takuji Okamoto, Hiroyuki Shibata, Kozo Kinoshita
    Design of High-Level Test Language for Digital LSI. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:508-513 [Conf]
  45. Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
    On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:83-89 [Conf]
  46. Xiaoqing Wen, Kozo Kinoshita
    Testable Designs of Sequential Circuits Under Highly Observable Condition. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:632-641 [Conf]
  47. Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
    Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:72-77 [Conf]
  48. Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa
    Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:329-334 [Conf]
  49. Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
    Test Transformation to Improve Compaction by Statistical Encoding. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:294-299 [Conf]
  50. Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
    A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:82-87 [Conf]
  51. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
    A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:58-65 [Conf]
  52. Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
    On Low-Capture-Power Test Generation for Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:265-270 [Conf]
  53. Hiroyuki Yotsuyanagi, Kozo Kinoshita
    Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:176-183 [Conf]
  54. Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
    Resynthesis for sequential circuits designed with a specified initial state. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:152-157 [Conf]
  55. C. Boswell, Kewal K. Saluja, Kozo Kinoshita
    Design of Programmable Logic Arrays for Parallel Testing. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 1985, v:1, n:1, pp:5-16 [Journal]
  56. Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
    Fault Diagnosis of Physical Defects Using Unknown Behavior Model. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:187-194 [Journal]
  57. Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
    Static test compaction for IDDQ testing of bridging faults in sequential circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2000, v:31, n:11, pp:41-50 [Journal]
  58. Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
    On invariant implication relations for removing partial circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:7, pp:39-47 [Journal]
  59. Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
    Built-in Self-Test for crosstalk faults in a digital VLSI. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:13, pp:35-47 [Journal]
  60. Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita
    IDDQ test vector selection for transistor short fault testing. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:5, pp:11-21 [Journal]
  61. Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita
    A diagnosis method for single logic design errors in gate-level combinational circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:6, pp:30-39 [Journal]
  62. Hideo Fujiwara, Kozo Kinoshita
    On the Computational Complexity of System Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:10, pp:881-885 [Journal]
  63. Hideo Fujiwara, Kozo Kinoshita
    Connection Assignments for Probabilistically Diagnosable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:3, pp:280-283 [Journal]
  64. Hideo Fujiwara, Kozo Kinoshita
    Some Existence Theorems for Probabilistically Diagnosable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:4, pp:379-384 [Journal]
  65. Hideo Fujiwara, Kozo Kinoshita
    A Design of Programmable Logic Arrays with Universal Tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:11, pp:823-828 [Journal]
  66. Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita
    Easily Testable Sequential Machines with Extra Inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:8, pp:821-826 [Journal]
  67. Kozo Kinoshita, Kewal K. Saluja
    Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:10, pp:862-870 [Journal]
  68. Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda
    On Magnetic Bubble Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:3, pp:247-253 [Journal]
  69. Kewal K. Saluja, Kozo Kinoshita
    Test Pattern Generation for API Faults in RAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:3, pp:284-287 [Journal]
  70. Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara
    An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:11, pp:1038-1046 [Journal]
  71. Tsutomu Sasao, Kozo Kinoshita
    Realization of Minimum Circuits with Two-Input Conservative Logic Elements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:8, pp:749-752 [Journal]
  72. Tsutomu Sasao, Kozo Kinoshita
    Cascade Realization of 3-Input 3-Output Conservative Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:3, pp:214-221 [Journal]
  73. Tsutomu Sasao, Kozo Kinoshita
    Conservative Logic Elements and Their Universality. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:9, pp:682-685 [Journal]
  74. Tsutomu Sasao, Kozo Kinoshita
    On the Number of Fanout-Free Functions and Unate Cascade Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:1, pp:66-72 [Journal]
  75. Xiaoqing Wen, Kozo Kinoshita
    A Testable Design of Logic Circuits under Highly Observable Condition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:5, pp:654-659 [Journal]
  76. Noriyoshi Itazaki, Kozo Kinoshita
    Test pattern generation for circuits with tri-state modules by Z-algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1327-1334 [Journal]
  77. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
    Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1496-1504 [Journal]
  78. Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita
    An approach to the analysis and detection of crosstalk faults in digital VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:387-395 [Journal]
  79. Yuzo Takamatsu, Kozo Kinoshita
    CONT: a concurrent test generation system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:966-972 [Journal]
  80. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
    Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:6, pp:613-620 [Journal]

  81. Design of partially parallel scan chain. [Citation Graph (, )][DBLP]


  82. Current-based testable design of level shifters in liquid crystal display drivers. [Citation Graph (, )][DBLP]


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