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Publications of Author

1. Hiroyuki Higuchi, Yusuke Matsunaga
   Enhancing the performance of multi-cycle path analysis in an industrial setting. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:192-197 [Conf]
   
2. Hiroyuki Higuchi, Yusuke Matsunaga
   Implicit prime compatible generation for minimizing incompletely specified finite state machines. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1995, pp:- [Conf]
   
3. Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
   A Resynthesis Approach for Network Optimization. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:458-463 [Conf]
   
4. Hiroyuki Higuchi, Yusuke Matsunaga
   A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:463-466 [Conf]
   
5. Yusuke Matsunaga
   An Efficient Equivalence Checker for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:629-634 [Conf]
   
6. Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton
   On Computing the Transitive Closure of a State Transition Relation. [Citation Graph (0, 0)][DBLP]
   DAC, 1993, pp:260-265 [Conf]
   
7. Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita
   Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
   DAC, 1990, pp:284-289 [Conf]
   
8. Fumihiro Maruyama, Taeko Kakuda, Yusuke Matsunaga, Yoriko Minoda, Shuho Sawada, Nobuaki Kawato
   co-LODEX: A Cooperative Expert System for Logic design. [Citation Graph (0, 0)][DBLP]
   FGCS, 1988, pp:1299-1306 [Conf]
   
9. Taeko Matsunaga, Yusuke Matsunaga
   Area minimization algorithm for parallel prefix adders under bitwise delay constraints. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:435-440 [Conf]
   
10. Masahiro Fujita, Yusuke Matsunaga
    Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:560-563 [Conf]
    
11. Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda
    Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:38-41 [Conf]
    
12. Yusuke Matsunaga
    On accelerating pattern matching for technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:118-122 [Conf]
    
13. Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda
    Multi-Level Logic Minimization Across Latch Boundaries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:406-409 [Conf]
    
14. Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita
    LP based cell selection with constraints of timing, area, and power consumption. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:378-381 [Conf]
    
15. Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga
    Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:179-186 [Conf]
    
16. Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga
    The statistical longest path problem and its application to delay analysis of logical circuits. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:134-139 [Conf]
    
17. Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga
    Variable ordering algorithms for ordered binary decision diagrams and their evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:6-12 [Journal]
    
18. Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki
    A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:466-476 [Journal]
    
19. Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi. Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura
    A character size optimization technique for throughput enhancement of character projection lithography. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
20. 
    Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. [Citation Graph (, )][DBLP]
    
    
21. 
    An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis. [Citation Graph (, )][DBLP]
    
    
22. 
    A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). [Citation Graph (, )][DBLP]
    
    
23. 
    An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. [Citation Graph (, )][DBLP]
    
    
24. 
    Synthesis of parallel prefix adders considering switching activities. [Citation Graph (, )][DBLP]