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Ramesh Karri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Inki Hong, Miodrag Potkonjak, Ramesh Karri
    Heterogeneous BISR-approach using System Level Synthesis Flexibility. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:289-294 [Conf]
  2. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault tolerant nanoelectronic processor architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:311-316 [Conf]
  3. Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu
    Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1192-1195 [Conf]
  4. Nikhil Joshi, Kaijie Wu, Ramesh Karri
    Concurrent Error Detection Schemes for Involution Ciphers. [Citation Graph (0, 0)][DBLP]
    CHES, 2004, pp:400-412 [Conf]
  5. Ramesh Karri, Grigori Kuznetsov, Michael Gössel
    Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers. [Citation Graph (0, 0)][DBLP]
    CHES, 2003, pp:113-124 [Conf]
  6. Bo Yang, Ramesh Karri
    Power optimization for universal hash function data path using divide-and-concatenate technique. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:219-224 [Conf]
  7. Aurobindo Dasgupta, Ramesh Karri
    Electromigration Reliability Enhancement via Bus Activity Distribution. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:353-356 [Conf]
  8. Aurobindo Dasgupta, Ramesh Karri
    Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:819-824 [Conf]
  9. Balakrishnan Iyer, Ramesh Karri
    Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:137-142 [Conf]
  10. Ramesh Karri, Alex Orailoglu
    Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:662-665 [Conf]
  11. Ramesh Karri, Alex Orailoglu
    High-Level Synthesis of Fault-Secure Microarchitectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:429-433 [Conf]
  12. Ramesh Karri, Alex Orailoglu
    Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:552-556 [Conf]
  13. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
    Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:579-585 [Conf]
  14. Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
    Synthesis of Application Specific Programmable Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:353-358 [Conf]
  15. Miodrag Potkonjak, Kyosun Kim, Ramesh Karri
    Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:252-257 [Conf]
  16. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Topology aware mapping of logic functions onto nanowire-based crossbar architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:723-726 [Conf]
  17. Bo Yang, Ramesh Karri, David A. McGrew
    Divide-and-concatenate: an architecture level optimization technique for universal hash functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:614-617 [Conf]
  18. Bo Yang, Kaijie Wu, Ramesh Karri
    Secure scan: a design-for-test architecture for crypto chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:135-140 [Conf]
  19. Kaijie Wu, Ramesh Karri
    Exploiting Idle Cycles for Algorithm Level Re-Computing. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:842-846 [Conf]
  20. Kyosun Kim, Kaijie Wu, Ramesh Karri
    owards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1214-1219 [Conf]
  21. Kaijie Wu, Ramesh Karri
    Idle Cycles Based Concurrent Error Detection of RC6 Encryption. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:200-205 [Conf]
  22. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
    Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:427-435 [Conf]
  23. Bo Yang, Nikhil Joshi, Ramesh Karri
    A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:280- [Conf]
  24. Bo Yang, Ramesh Karri, David A. McGrew
    Divide and concatenate: a scalable hardware architecture for universal MAC. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:258- [Conf]
  25. Ramesh Karri, Alex Orailoglu
    Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:519-526 [Conf]
  26. Ramesh Karri, Alex Orailoglu
    Optimal Self-Recovering Microarchitecture Synthesis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:512-521 [Conf]
  27. Inki Hong, Miodrag Potkonjak, Ramesh Karri
    Power optimization using divide-and-conquer techniques for minimization of the number of operations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:108-111 [Conf]
  28. Balakrishnan Iyer, Ramesh Karri, Israel Koren
    Phantom redundancy: a high-level synthesis approach for manufacturability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:658-661 [Conf]
  29. Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
    Heterogeneous built-in resiliency of application specific programmable processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:406-411 [Conf]
  30. Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
    Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:33-38 [Conf]
  31. Kaijie Wu, Ramesh Karri
    Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:537-0 [Conf]
  32. Alex Orailoglu, Ramesh Karri
    High-Level Synthesis of Self-Recovering MicroArchitectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:286-289 [Conf]
  33. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:533-542 [Conf]
  34. Sergei Sokolov, Ramesh Karri
    Allocation and Binding During Fault-Secure Microarchitecture Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:327-330 [Conf]
  35. Vitalij Ocheretnij, G. Kouznetsov, Ramesh Karri, Michael Gössel
    On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:141-146 [Conf]
  36. Aurobindo Dasgupta, Ramesh Karri
    Synthesis of Reliable Application Specific Heterogeneous Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1215-1218 [Conf]
  37. Aurobindo Dasgupta, Ramesh Karri
    Simultaneous scheduling and binding for power minimization during microarchitecture synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:69-74 [Conf]
  38. Ramesh Karri, Grigori Kuznetsov, Michael Gössel
    Parity-Based Concurrent Error Detection in Symmetric Block Ciphers. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:919-926 [Conf]
  39. Ramesh Karri, Nilanjan Mukherjee
    Versatile BIST: an integrated approach to on-line/off-line BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:910-917 [Conf]
  40. Ramesh Karri, Kaijie Wu
    Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:971-978 [Conf]
  41. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:472-478 [Conf]
  42. Charles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri, I. Kim, S. Roy, S. Wu
    A Parameterized VHDL Library for On-Line Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:479-488 [Conf]
  43. Kaijie Wu, Ramesh Karri
    Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:221-229 [Conf]
  44. Kaijie Wu, Ramesh Karri
    Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:902-911 [Conf]
  45. Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Gössel
    Low Cost Concurrent Error Detection for the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1242-1248 [Conf]
  46. Bo Yang, Kaijie Wu, Ramesh Karri
    Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:339-344 [Conf]
  47. Ramesh Karri, Alex Orailoglu
    ALPS: An Algorithm for Pipeline Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:124-132 [Conf]
  48. Ramesh Karri, Piyush Mishra
    Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:358-368 [Conf]
  49. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:214-221 [Conf]
  50. Ramesh Karri, Karin Högstedt, Alex Orailoglu
    Computer-Aided Design of Fault-Tolerant VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:88-96 [Journal]
  51. Ramesh Karri, Michael Nicolaidis
    Guest Editors' Introduction: Online VLSI Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:12-16 [Journal]
  52. Alex Orailoglu, Ramesh Karri
    Synthesis of fault-tolerant and real-time microarchitectures. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 1994, v:25, n:1, pp:73-84 [Journal]
  53. Ramesh Karri, Piyush Mishra
    Optimizing the Energy Consumed by Secure Wireless Sessions - Wireless Transport Layer Security Case Study. [Citation Graph (0, 0)][DBLP]
    MONET, 2003, v:8, n:2, pp:177-185 [Journal]
  54. Nikhil Joshi, Jayachandran Sundararajan, Kaijie Wu, Bo Yang, Ramesh Karri
    Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:10, pp:1230-1239 [Journal]
  55. Ramesh Karri, Kyosun Kim, Miodrag Potkonjak
    Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:11, pp:1272-1284 [Journal]
  56. Alex Orailoglu, Ramesh Karri
    Automatic Synthesis of Self-Recovering VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:2, pp:131-142 [Journal]
  57. Aurobindo Dasgupta, Ramesh Karri
    High-reliability, low-energy microarchitecture synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1273-1280 [Journal]
  58. Ramesh Karri
    Guest editor's introduction to special section on high-level design validation and test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:353-354 [Journal]
  59. Ramesh Karri, Balakrishnan Iyer, Israel Koren
    Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:877-888 [Journal]
  60. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
    Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1509-1517 [Journal]
  61. Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri
    Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1163-1169 [Journal]
  62. Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
    Micropreemption synthesis: an enabling mechanism for multitask VLSI systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:19-30 [Journal]
  63. Kaijie Wu, Ramesh Karri
    Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1077-1087 [Journal]
  64. Kaijie Wu, Ramesh Karri
    Fault secure datapath synthesis using hybrid time and hardware redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1476-1485 [Journal]
  65. Kaijie Wu, Ramesh Karri
    Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:413-422 [Journal]
  66. Bo Yang, Ramesh Karri, David A. McGrew
    Divide-and-concatenate: an architecture-level optimization technique for universal hash functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1740-1747 [Journal]
  67. Bo Yang, Kaijie Wu, Ramesh Karri
    Secure Scan: A Design-for-Test Architecture for Crypto Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2287-2293 [Journal]
  68. Inki Hong, Miodrag Potkonjak, Ramesh Karri
    Power optimization using divide-and-conquer techniques for minimization of the number of operations. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:4, pp:405-429 [Journal]
  69. Ramesh Karri, Balakrishnan Iyer
    Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:505-515 [Journal]
  70. Darshan Sonecha, Bo Yang, Ramesh Karri, David A. McGrew
    High speed architectures for Leviathan: a binary tree based stream cipher. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:10, pp:573-584 [Journal]
  71. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:865-869 [Conf]
  72. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:216-224 [Conf]
  73. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:63-68 [Conf]
  74. Inki Hong, Miodrag Potkonjak, Ramesh Karri
    A heterogeneous built-in self-repair approach using system-level synthesis flexibility. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2004, v:53, n:1, pp:93-101 [Journal]
  75. Kaijie Wu, Ramesh Karri
    Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:501-511 [Journal]
  76. Alex Orailoglu, Ramesh Karri
    Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:304-311 [Journal]
  77. Ramesh Karri, Kaijie Wu
    Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:864-875 [Journal]
  78. Kaijie Wu, Piyush Mishra, Ramesh Karri
    Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:31-39 [Journal]
  79. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Towards Nanoelectronics Processor Architectures. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:235-254 [Journal]

  80. Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. [Citation Graph (, )][DBLP]


  81. Logic Mapping in Crossbar-Based Nanoarchitectures. [Citation Graph (, )][DBLP]


  82. Attacks and Defenses for JTAG. [Citation Graph (, )][DBLP]


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