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Cheng-Wen Wu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jin-Hua Hong, Cheng-Wen Wu
    Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:565-570 [Conf]
  2. Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
    A programmable built-in self-test core for embedded memories. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:11-12 [Conf]
  3. Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu
    SRAM delay fault modeling and test algorithm development. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:104-109 [Conf]
  4. Chi-Feng Wu, Cheng-Wen Wu
    Testing Interconnects of Dynamic Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:279-282 [Conf]
  5. Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu
    A configurable AES processor for enhanced security. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:361-366 [Conf]
  6. Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    Design and test of a scalable security processor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:372-375 [Conf]
  7. Ching-Hong Tsai, Cheng-Wen Wu
    Processor-programmable memory BIST for bus-connected embedded memories. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:325-330 [Conf]
  8. Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
    An HMAC processor with integrated SHA-1 and MD5 algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:456-458 [Conf]
  9. Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu
    RSA cryptosystem design based on the Chinese remainder theorem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:391-395 [Conf]
  10. Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen
    Flash Memory Die Sort by a Sample Classification Method. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:182-187 [Conf]
  11. Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
    Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:91-96 [Conf]
  12. Yu-Chun Chuang, Cheng-Wen Wu
    On-Line Error Detection Schemes for a Systolic Finite-Field Inverter. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:301-305 [Conf]
  13. Lijian Li, Xiaoyang Yu, Cheng-Wen Wu, Yinghua Min
    A waveform simulator based on Boolean process. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:145-150 [Conf]
  14. Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu
    On-chip Analog Response Extraction with 1-Bit ? - Modulators. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:49-0 [Conf]
  15. Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu
    Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:50-55 [Conf]
  16. Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng
    A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:62-67 [Conf]
  17. Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling and Test Access Architecture Optimization for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:411-0 [Conf]
  18. Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu
    Defect Oriented Fault Analysis for SRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:256-261 [Conf]
  19. Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu
    An FPGA-based re-configurable functional tester for memory chips. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:51-57 [Conf]
  20. Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang
    Fail Pattern Identification for Memory Built-In Self-Repair. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:366-371 [Conf]
  21. Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu
    On Test and Diagnostics of Flash Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:260-265 [Conf]
  22. Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu
    Defect Level Prediction Using Multi-Model Fault Coverage. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:301-0 [Conf]
  23. Shyue-Kung Lu, Jeh-Sheng Shih, Cheng-Wen Wu
    A Testable/Fault Tolerant FFT Processor Design. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:429-0 [Conf]
  24. Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
    A MISR Computation Algorithm for Fast Signature Simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:213-218 [Conf]
  25. Cheng-Wen Wu
    On energy efficiency of VLSI testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:132-137 [Conf]
  26. Cheng-Wen Wu
    Testing Embedded Memories: Is BIST the Ultimate Solution?. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:516-517 [Conf]
  27. Cheng-Wen Wu, Chih-Yuang Su
    A Probabilistic Model for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:70-75 [Conf]
  28. Yeong-Ruey Shieh, Cheng-Wen Wu
    DC control and observation structures for analog circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:120-126 [Conf]
  29. Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu
    A Processor-Based Built-In Self-Repair Design for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:366-371 [Conf]
  30. Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling of BISTed Memory Cores for SOC. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:356-0 [Conf]
  31. Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
    A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:103-0 [Conf]
  32. Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
    A built-in self-test and self-diagnosis scheme for embedded SRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:45-50 [Conf]
  33. Cheng-Wen Wu, Peter R. Cappello
    Application-Specific CAD of High-Throughout IIR Filters. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1987, pp:302-305 [Conf]
  34. Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
    A network security processor design based on an integrated SOC design and test platform. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:490-495 [Conf]
  35. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
    Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:301-306 [Conf]
  36. Jin-Fu Li, Cheng-Wen Wu
    Memory fault diagnosis by syndrome compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:97-101 [Conf]
  37. Juin-Ming Lu, Cheng-Wen Wu
    Cost and Benefit Models for Logic and Memory BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:710-714 [Conf]
  38. Cheng-Wen Wu
    SOC Testing Methodology and Practice. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1120-1121 [Conf]
  39. Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Ping Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
    A Hierarchical Test Scheme for System-On-Chip Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:486-490 [Conf]
  40. Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
    Flash Memory Built-In Self-Test Using March-Like Algorithm. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:137-141 [Conf]
  41. Jin-Fu Li, Cheng-Wen Wu
    Testable and Fault Tolerant Design for FFT Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:201-209 [Conf]
  42. Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai
    BRAINS: A BIST Compiler for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:299-0 [Conf]
  43. Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu
    Failure Factor Based Yield Enhancement for SRAM Designs. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:20-28 [Conf]
  44. Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
    An Application-Independent Delay Testing Methodology for Island-Style FPGA. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:478-486 [Conf]
  45. Chin-Lung Su, Yi-Ting Yeh, Cheng-Wen Wu
    An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:81-92 [Conf]
  46. Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
    RAMSES: A Fast Memory Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:165-173 [Conf]
  47. Yih-Lang Li, Cheng-Wen Wu
    Logic and Fault Simulation by Cellular Automata. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:552-556 [Conf]
  48. Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
    FAME: A Fault-Pattern Based Memory Failure Analysis Framework. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:595-598 [Conf]
  49. Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
    Error Catch and Analysis for Semiconductor Memories Using March Tests. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:468-471 [Conf]
  50. Cheng-Wen Wu, Shyue-Kung Lu
    Designing Self-Testable Cellular Arrays. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:110-113 [Conf]
  51. Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
    A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:262-0 [Conf]
  52. Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang
    Combinational circuit fault diagnosis using logic emulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:549-552 [Conf]
  53. Cheng-Wen Wu, Yung-Fa Chou
    General Modular Multiplication by Block Multiplication and Table Lookup. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:295-298 [Conf]
  54. Shyue-Kung Lu, Cheng-Wen Wu
    A novel approach to testing LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:173-177 [Conf]
  55. Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
    Diagonal Test and Diagnostic Schemes for Flash Memorie. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:37-46 [Conf]
  56. Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    March-based RAM diagnosis algorithms for stuck-at and coupling faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:758-767 [Conf]
  57. Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow
    A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:393-402 [Conf]
  58. Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu
    MRAM Defect Analysis and Fault Modeli. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:124-133 [Conf]
  59. Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
    Fault Pattern Oriented Defect Diagnosis for Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:29-38 [Conf]
  60. Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu
    A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:65-69 [Conf]
  61. Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu
    Fault-Pattern Oriented Defect Diagnosis for Flash Memory. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:3-8 [Conf]
  62. Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li
    A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:53-0 [Conf]
  63. Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
    A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:68-0 [Conf]
  64. Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
    Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:225-230 [Conf]
  65. Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
    RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:281-288 [Conf]
  66. Cheng-Wen Wu
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:128-129 [Conf]
  67. Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu
    A Built-In Self-Repair Scheme for NOR-Type Flash Memory. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:114-119 [Conf]
  68. Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
    Testing and Diagnosing Embedded Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:389-394 [Conf]
  69. Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    Test and Diagnosis of Word-Oriented Multiport Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:248-253 [Conf]
  70. Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu
    A BIST Scheme for FPGA Interconnect Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:201-206 [Conf]
  71. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
    Simulation-Based Test Algorithm Generation for Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:291-296 [Conf]
  72. Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin
    Flash Memory Built-In Self-Diagnosis with Test Mode Control. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:15-20 [Conf]
  73. Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu
    SDRAM Delay Fault Modeling and Performance Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:53-58 [Conf]
  74. Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
    A Programmable BIST Core for Embedded DRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:1, pp:59-70 [Journal]
  75. Bin-Hong Lin, Cheng-Wen Wu, Hwei-Tsu Ann Luh
    Efficient and Economical Test Equipment Setup Using Procorrelation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:34-43 [Journal]
  76. Yeong-Ruey Shieh, Cheng-Wen Wu
    Control and Observation Structures for Analog Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:2, pp:56-64 [Journal]
  77. Wen-Feng Chang, Cheng-Wen Wu
    Does There Exist a Combinational TSC Checker for 1/3 Code Using Only Primitive Gates? [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1997, v:13, n:4, pp:681-695 [Journal]
  78. Wen-Feng Chang, Cheng-Wen Wu
    TSC Berger-Code Checker Design for 2r-1-Bit Information. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1999, v:15, n:3, pp:429-440 [Journal]
  79. Shih-Arn Hwang, Cheng-Wen Wu
    Test Energy Minimization for C-Testable ILAs. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1999, v:15, n:6, pp:899-911 [Journal]
  80. Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu
    Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2003, v:19, n:4, pp:571-587 [Journal]
  81. Shao-Hui Shieh, Cheng-Wen Wu
    Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2003, v:19, n:6, pp:1015-1039 [Journal]
  82. Chih-Yuang Su, Cheng-Wen Wu
    A Probabilistic Model for Path Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:783-794 [Journal]
  83. Kun-Jin Lin, Cheng-Wen Wu
    Easily Testable Cellular Array Multipliers. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1991, v:7, n:3, pp:367-383 [Journal]
  84. Cheng-Wen Wu
    Relating Tiling and Coloring to Testing of Combinational Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1990, v:6, n:1, pp:63-72 [Journal]
  85. Cheng-Wen Wu, Jiann-Yuan Choue
    Fault-Tolerant FFT Butterfly Network Design. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1993, v:9, n:1, pp:137-150 [Journal]
  86. Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu
    VLSI Design of RSA Cryptosystem Based on the Chinese Remainder Theorem. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2001, v:17, n:6, pp:967-980 [Journal]
  87. Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
    A Hierarchical Test Methodology for Systems on Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:5, pp:69-81 [Journal]
  88. Wen-Feng Chang, Cheng-Wen Wu
    Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:8, pp:815-826 [Journal]
  89. Kun-Jin Lin, Cheng-Wen Wu
    A Low-Power CAM Design for LZ Data Compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:10, pp:1139-1145 [Journal]
  90. Shyue-Kung Lu, Sy-Yen Kuo, Cheng-Wen Wu
    Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:9, pp:1028-1034 [Journal]
  91. Shih-Yuang Su, Cheng-Wen Wu
    Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:495-501 [Journal]
  92. Cheng-Wen Wu, Peter R. Cappello
    Easily Testable Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:5, pp:640-652 [Journal]
  93. Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
    Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1328-1336 [Journal]
  94. Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu
    Sequential circuit fault simulation using logic emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:724-736 [Journal]
  95. Yih-Lang Li, Cheng-Wen Wu
    Cellular automata for efficient parallel logic and fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:740-749 [Journal]
  96. Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
    A fast signature computation algorithm for LFSR and MISR. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1031-1040 [Journal]
  97. Kun-Jin Lin, Cheng-Wen Wu
    Testing content-addressable memories using functional fault modelsand march-like algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:577-588 [Journal]
  98. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
    Fault simulation and test algorithm generation for random accessmemories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:480-490 [Journal]
  99. Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu
    A built-in self-repair design for RAMs with 2-D redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:742-745 [Journal]
  100. Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu
    Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:34-42 [Journal]
  101. Cheng-Wen Wu
    SOC Testing Methodology and Practice [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  102. Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
    Built-in redundancy analysis for memory yield improvement. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:386-399 [Journal]
  103. Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
    STEAC: A Platform for Automatic SOC Test Integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:541-545 [Journal]
  104. Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu
    C-testable design techniques for iterative logic arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:146-152 [Journal]
  105. Chih-Yuang Su, Shih-Am Hwang, Po-Song Chen, Cheng-Wen Wu
    An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:280-284 [Journal]
  106. Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu
    Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:503-516 [Journal]
  107. Shih-Arn Hwang, Cheng-Wen Wu
    Unified VLSI systolic array design for LZ data compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:489-499 [Journal]
  108. Jin-Fu Li, Cheng-Wen Wu
    Efficient FFT network testing and diagnosis schemes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:267-278 [Journal]
  109. Jin-Hua Hong, Cheng-Wen Wu
    Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:474-484 [Journal]

  110. Test Integration for SOC Supporting Very Low-Cost Testers. [Citation Graph (, )][DBLP]


  111. On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. [Citation Graph (, )][DBLP]


  112. Fast identification of operating current for toggle MRAM by spiral search. [Citation Graph (, )][DBLP]


  113. An error tolerance scheme for 3D CMOS imagers. [Citation Graph (, )][DBLP]


  114. High-speed C-testable systolic array design for Galois-field inversion. [Citation Graph (, )][DBLP]


  115. An adaptive code rate EDAC scheme for random access memory. [Citation Graph (, )][DBLP]


  116. A low-cost and scalable test architecture for multi-core chips. [Citation Graph (, )][DBLP]


  117. Economic Aspects of Memory Built-in Self-Repair. [Citation Graph (, )][DBLP]


  118. Raisin: Redundancy Analysis Algorithm Simulation. [Citation Graph (, )][DBLP]


  119. A Systematic Approach to Memory Test Time Reduction. [Citation Graph (, )][DBLP]


  120. Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. [Citation Graph (, )][DBLP]


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