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Toshinori Hosokawa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta
    Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:485-491 [Conf]
  2. Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka
    Design for testability using register-transfer level partial scan selection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka
    A SoC Test Strategy Based on a Non-Scan DFT Method. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:305-310 [Conf]
  4. Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
    A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:55-60 [Conf]
  5. Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara
    A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:130-135 [Conf]
  6. Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara
    Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:192-0 [Conf]
  7. Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu
    A Partial Scan Design Method Based on n-Fold Line-up Structures. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:306-0 [Conf]
  8. Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka
    A Design for testability Method Using RTL Partitioning. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:88-93 [Conf]
  9. Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara
    An Effective Design for Hierarchical Test Generation Based on Strong Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:288-293 [Conf]
  10. Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara
    An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:190-197 [Conf]
  11. Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
    A DFT Selection Method for Reducing Test Application Time of System-on-Chips. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:412-417 [Conf]
  12. Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta
    A Test Point Insertion Method to Reduce the Number of Test Patterns. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:298-304 [Conf]
  13. Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin
    A State Traversal Algorithm Using a State Covariance Matrix. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:97-101 [Conf]
  14. Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
    A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:328-335 [Conf]
  15. Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara
    Test sequence compaction methods for acyclic sequential circuits using a time expansion model. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:10, pp:105-115 [Journal]

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