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Mitsuyasu Ohta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta
    Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:485-491 [Conf]
  2. Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka
    Design for testability using register-transfer level partial scan selection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu
    A Partial Scan Design Method Based on n-Fold Line-up Structures. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:306-0 [Conf]
  4. Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka
    A Design for testability Method Using RTL Partitioning. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:88-93 [Conf]
  5. Tetsuji Kishi, Mitsuyasu Ohta, Takashi Taniguchi, Hiroshi Kadota
    A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:462- [Conf]
  6. Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta
    A Test Point Insertion Method to Reduce the Number of Test Patterns. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:298-304 [Conf]
  7. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta
    On validating data hold times for flip-flops in sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:317-325 [Conf]

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