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William H. Kao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao
    A new congestion-driven placement algorithm based on cell inflation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:605-608 [Conf]
  2. Bogdan G. Arsintescu, Edoardo Charbon, Enrico Malavasi, Umakanta Choudhury, William H. Kao
    General AC Constraint Transformation for Analog ICs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:38-43 [Conf]
  3. William H. Kao, Nader Fathi, Chia-Hao Lee
    Algorithms for automatic transistor sizing in CMOS digital circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:781-784 [Conf]
  4. William H. Kao, Wenkung K. Chu
    Noise constraint driven placement for mixed signal designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:712-715 [Conf]
  5. Junwei Hou, William H. Kao, Abhijit Chatterjee
    A novel concurrent fault simulation method for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:448-451 [Conf]
  6. Stephen C. Bateman, William H. Kao
    Simulation of an Integrated Design and Test Environment for Mixed-Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:405-414 [Conf]
  7. Ramakrishna Voorakaranam, Sudip Chakrabarti, Junwei Hou, Alfred V. Gomes, Sasikumar Cherubal, Abhijit Chatterjee, William H. Kao
    Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:903-912 [Conf]
  8. William H. Kao, Xiaopeng Dong
    Digital Block Modeling and Substrate Noise Aware Floorplanning for Mixed Signal SOCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1935-1938 [Conf]

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