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Jinn-Shyan Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang
    A new CMAC neural network architecture and its ASIC realization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:481-484 [Conf]
  2. Yi-Ming Wang, Jinn-Shyan Wang
    A reliable low-power fast skew-compensation circuit. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:547-548 [Conf]
  3. Jinn-Shyan Wang, Po-Hui Yang
    Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:225-228 [Conf]
  4. Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang
    Technnology Mapping for Low Power. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:145-148 [Conf]
  5. Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang
    Charge sharing fault analysis and testing for CMOS domino logic circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:435-440 [Conf]
  6. Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang
    Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:62-67 [Conf]
  7. Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang
    A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:239-243 [Conf]
  8. Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
    An 830mW, 586kbps 1024-bit RSA chip design. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:24-29 [Conf]
  9. Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone
    Charge Sharing Fault Detection for CMOS Domino Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:77-85 [Conf]
  10. Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
    Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:329-337 [Conf]
  11. Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang
    Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:387-390 [Conf]
  12. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh
    A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:1683-1686 [Conf]
  13. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang
    An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4517-4520 [Conf]
  14. Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu
    Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1572-1575 [Conf]
  15. Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang
    An all-digital pulsewidth control loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1258-1261 [Conf]
  16. Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh
    A low-power high-SFDR CMOS direct digital frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1670-1673 [Conf]
  17. Sheng-Yeh Lai, Jinn-Shyan Wang
    A high-efficiency CMOS charge pump circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:406-409 [Conf]
  18. Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang
    A high-speed CMOS incrementer/decrementer. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:88-91 [Conf]
  19. Ching-Rong Chang, Jinn-Shyan Wang
    A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:254-257 [Conf]
  20. Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang
    A cell selection strategy for low power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:416-419 [Conf]
  21. Yi-Ming Wang, Jinn-Shyan Wang
    An all-digital 50% duty-cycle corrector. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:925-928 [Conf]
  22. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen
    A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:141-144 [Conf]
  23. Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh
    Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:401-404 [Conf]
  24. Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo
    An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:155-160 [Conf]
  25. Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang
    Low-power fixed-width array multipliers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:307-312 [Conf]
  26. Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng
    Low-power embedded SRAM macros with current-mode read/write operations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:282-287 [Conf]
  27. Yuan-Pao Hsu, Kao-Shing Hwang, Jinn-Shyan Wang
    An Associative Architecture of CMAC for Mobile Robot Motion Control. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2002, v:18, n:2, pp:145-161 [Journal]
  28. Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang
    Energy Efficient Caching-on-Cache Architectures for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2003, v:19, n:5, pp:809-825 [Journal]
  29. Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
    Charge-sharing alleviation and detection for CMOS domino circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:266-280 [Journal]
  30. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang
    A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:4, pp:472-483 [Journal]
  31. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen
    An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:5, pp:704-715 [Journal]
  32. Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen
    Design theory and implementation for low-power segmented bus systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:38-54 [Journal]
  33. Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu
    Design of STR level converters for SoCs using the multi-island dual-VDD design technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  34. Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo
    A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  35. Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chai Liu
    An improved SAR controller for DLL applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, T. F. Chen
    Segmented bus design for low-power systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:25-29 [Journal]

  37. A dynamic quality-scalable H.264 video encoder chip. [Citation Graph (, )][DBLP]


  38. No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. [Citation Graph (, )][DBLP]


  39. A Condition-based Intra Prediction Algorithm for H.264/AVC. [Citation Graph (, )][DBLP]


  40. A low-voltage latch-adder based tree multiplier. [Citation Graph (, )][DBLP]


  41. A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. [Citation Graph (, )][DBLP]


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